Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

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A Video display simulator

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CHIP-8 console on FPGA

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Notes on the Red Pitaya Open Source Instrument

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karuta

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

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Mutual labels: fpga, verilog

vga-clock

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

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Mutual labels: fpga, verilog

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

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Mutual labels: fpga, verilog

Fpga readings

Recipe for FPGA cooking

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FpOC

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

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Mutual labels: fpga, verilog

Biriscv

32-bit Superscalar RISC-V CPU

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Tools for running FPGA vendor toolchains with Docker

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SpinalDev

Docker Development Environment for SpinalHDL

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CNN acceleration on virtex-7 FPGA with verilog HDL

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yafpgatetris

Yet Another Tetris on FPGA Implementation

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vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

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xeda

Cross EDA Abstraction and Automation

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FPGA NTP SERVER

A FPGA implementation of the NTP and NTS protocols

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Mutual labels: fpga, verilog

gateware-ts

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

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Mutual labels: fpga, verilog

hdl-tools

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Small Processing Unit 32: A compact RV32I CPU written in Verilog

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An Open Source configuration of the Arty platform

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Implementation of a Tensor Processing Unit for embedded systems and the IoT.

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Logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

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dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

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Mutual labels: fpga, fft

Openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

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Verilog Generator Of Neural Net Digit Detector For Fpga

Verilog Generator of Neural Net Digit Detector for FPGA

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FPGA/hardware design of openwifi

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All open source file and project for OpenFPGAduino project

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sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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eddr3

mirror of https://git.elphel.com/Elphel/eddr3

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Bazel build rules for Verilator

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dbgbus

A collection of debugging busses developed and presented at zipcpu.com

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kianRiscV

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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Mutual labels: fpga, verilog

Basic verilog

Must-have verilog systemverilog modules

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FPGA ThreeLevelStorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

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Mutual labels: fpga, verilog

svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!