342 Open source projects that are alternatives of or similar to Ice40 Playground

An FPGA based GDROM emulator for the Sega Dreamcast

A Video display simulator

Connectal is a framework for software-driven hardware development.

Dreamcast HDMI

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

NES in Verilog

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

FuseSoC-based SoC for SweRV EH1

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

浙江大学计算机体系结构课程实验

LicheeTang 蜂鸟E203 Core

SystemVerilog linter

SystemVerilog language server

GPGPU microprocessor architecture

All open source file and project for OpenFPGAduino project

Ham Radio hat for Raspberry PI

i8080 precise replica in Verilog, based on reverse engineering of real die

A low pin count sniffer for ICEStick - targeting TPM chips

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

IC design and development should be faster，simpler and more reliable

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

RePlAce global placement tool

A single-wire bi-directional chip-to-chip interface for FPGAs

PicoRV32 - A Size-Optimized RISC-V CPU

A convolutional neural network implemented in hardware (verilog)

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Repurposing existing HDL tools to help writing better code

A Verilog implementation of DisplayPort protocol for FPGAs

Verilog module for calculation of FFT.

iCESugar FPGA Board (base on iCE40UP5k)

A List of Free and Open Source Hardware Verification Tools and Frameworks

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

A 32-bit Microcontroller featuring a RISC-V core

A simple, basic, formally verified UART controller

Pano Logic G2 Reverse Engineering Project

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

Light-weight RISC-V RV32IMC microcontroller core.

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Verilog version of Z-scale (deprecated)

Compact FPGA game console

🌱 ❄️ Collection of open-source peripherals in Verilog

FPGA implementation of Cellular Neural Network (CNN)

Core description files for FuseSoC

Regression test suite for Icarus Verilog.

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

A nicer HDL.

Test suite designed to check compliance with the SystemVerilog standard.

Bitcoin miner for Xilinx FPGAs

All code found on nandland is here. underconstruction.gif

A utility for Composing FPGA designs from Peripherals

Chisel 3: A Modern Hardware Design Language

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器