252 Open source projects that are alternatives of or similar to Quasar

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Chisel Things for OFDM

Rocket Chip Generator

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Chisel 3: A Modern Hardware Design Language

SweRV EH1 core

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

SweRV EL2 Core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

⛔ DEPRECATED ⛔ HERO Software Development Kit

Documentatin for YatCPU

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Virtio implementation in SystemVerilog

FPGA-based RISC-V CPU+SoC.

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

ARV: Asynchronous RISC-V Go High-level Functional Model

Provides dot visualizations of chisel/firrtl circuits

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Simple RISC-V 3-stage Pipeline in Chisel

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

SoC based on VexRiscv and ICE40 UP5K

Facilitates building open source tools for working with hardware description languages (HDLs)

RISC-V processor emulator written in Rust+WASM

Yet another toy CPU.

high-performance RTL simulator

A right-to-left theme for Jekyll with Jalali support and some other goodies.

Add right-to-left support to the NativeScript framework

RISC-V SystemC-TLM simulator

An opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)

A kernel written in Rust

Stream analysis for xenon TPCs

RTL version of materializecss framework v1.0.0

RTL layout for Laravel Nova.

Awesome ASIC design verification

A collection of phase locked loop (PLL) related projects

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

Convert Java Types to TypeScript

Simple way to set RTL for materializecss.com.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

EVEREST: e-Versatile Research Stick for peoples

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

MDEPX — A BSD-style RTOS

OOUI is a modern JavaScript UI library with strong cross-browser support. It is the standard library for MediaWiki and Wikipedia. This is a mirror from https://gerrit.wikimedia.org. Main website:

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

Leeneon is a free portfolio template designed and developed to be accessible for as many users as possible.

An Open Source configuration of the Arty platform

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Intermediate Language (IL) for Hardware Accelerator Generators

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

RISCV SoftCPU Contest 2018

Laravel localization package for wrapping routes in multiple locale prefixes

The Gee (寂) Operating System, written in YuLang.

Wishbone controlled I2C controllers

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

RISC-V RV32I[MAC] emulator with ELF support

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

FIPS and higher-level algorithm tests for RISC-V Crypto Extension