854 Open source projects that are alternatives of or similar to Riscboy

FPGA-based RISC-V CPU+SoC.

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

LicheeTang 蜂鸟E203 Core

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

🎮 Gameboy link cable breakout PCB

Small Processing Unit 32: A compact RV32I CPU written in Verilog

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Yet Another RISC-V Implementation

Board layout for an eeprom powered GB cartridge

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

a simple and cheap vector network analyzer, including support software

Compact FPGA game console

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

No-MMU Linux capable RISC-V SoC designed to be useful.

Yet another toy CPU.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

List of ideas for getting started with TimVideos projects

Homebrew game for homebrew FPGA game console

SweRV EL2 Core

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

RISC-V processor emulator written in Rust+WASM

SweRV EH1 core

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

F# RISC-V Instruction Set formal specification

RISC-V CPU Core

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

All CPU and MCU documentation in one place

Simple, orthogonal 32-bit computer architecture and environment

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

RISC-V Cores, SoC platforms and SoCs

Managed Machine Learning Systems and Internet of Things Live Lesson

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Riscv32 CPU Project

A simple three-stage RISC-V CPU

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

A reimplementation of a tiny stack CPU

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Human Resource Machine - CPU Design #HRM

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

A low cost FPGA development board for absolute newbies

A small, light weight, RISC CPU soft core

A MIPS CPU implemented in Verilog

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

RISC-V Cores, SoC platforms and SoCs

A FPGA friendly 32 bit RISC-V CPU implementation

A mixed signal netlist language (pre-alpha)

Automatically set GOMAXPROCS to match Linux container CPU quota.

A Video display simulator

The Antikernel operating system project