143 Open source projects that are alternatives of or similar to Scaffold

VHDL compiler and simulator

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

Community created parallella projects

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

An abstraction library for interfacing EDA tools

VHDL-Mips-Pipeline-Microprocessor

VCD file (Value Change Dump) command line viewer

A work-in-progress for what is to be a software-free web server for static content.

GameCube Digital AV converter

VHDL-2008 Support Library

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Arduino MIPI DSI Shield

A Audio Interface for the Zedboard

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Scripts to build and use docker images including GHDL

An implementation of original SHA-256 hash function in (RTL) VHDL

A list of VHDL codes implementing cryptographic algorithms

Experimental compiler for a subset of Haskell to VHDL

This repository contains synthesizable examples which use the PoC-Library.

Scala based HDL

Parallella board design files

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

AES-128 hardware implementation

Hardware Description Languages

Haskell to VHDL/Verilog/SystemVerilog compiler

A tiny Open POWER ISA softcore written in VHDL 2008

VHDL for basic floating-point operations.

Core sources and tools for the MIST board

Digital FM Radio Receiver for FPGA

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

HashVoodoo FPGA Bitcoin Miner

HAL – The Hardware Analyzer

Acorn BBC Micro on an Altera DE1 FPGA board

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

A simple three-stage RISC-V CPU

Example code for the Numato Opsis board, the first HDMI2USB production board.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

ECE368 | Lab

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

List of ideas for getting started with TimVideos projects

A package for Sublime Text that aids coding in the VHDL language.

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

🔌 Hardware Abstraction Library in Python

Simple custom computer on a FPGA

GPL v3 2D/3D graphics engine in verilog

VHDL Samples

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

Image Processing Toolbox in Verilog using Basys3 FPGA

AXI PSRAM Controller IP for use with Digilent Nexys 4

VUnit is a unit testing framework for VHDL/SystemVerilog