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All Programming Languages → Verilog

Top 626 Verilog open source projects

201. RISCV Piccolo v1

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

✭ 29

Verilog c perl assembly Makefile C++SystemVerilog

202. thinpad top

Project template for Artix-7 based Thinpad board

✭ 39

Verilog c SystemVerilog python tcl

203. jetson-rdma-picoevb

Minimal HW-based demo of GPUDirect RDMA on NVIDIA Jetson AGX Xavier running L4T

✭ 95

tcl c Verilog shell Cuda Makefile

204. RFNoC-HLS-WINLAB

No description, website, or topics provided.

✭ 15

C++SystemVerilog Verilog c Makefile tcl

205. test jpeg

This is a myhdl test environment for the open-cores jpeg_encoder.

✭ 14

Verilog VHDL python

206. nysa

FPGA Development toolset

✭ 17

python Verilog

207. DSLogic-hdl

An open source FPGA design for DSLogic

✭ 99

Verilog

208. Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

✭ 68

Verilog scala cpu fpga chisel riscv

209. sdl

No description, website, or topics provided.

✭ 40

V Verilog Coq

210. BeebFpga

No description, website, or topics provided.

✭ 35

VHDL c Verilog tcl assembly shell

211. RiverRaidFPGA

River Raid game on FPGA

✭ 20

Verilog SystemVerilog Mathematica

212. cynth

a simple C-to-Verilog compiler

✭ 46

scala Verilog c

213. usbcorev

A full-speed device-side USB peripheral core written in Verilog.

✭ 135

Verilog python fpga usb verilog

214. parser

Derived from https://sourceforge.net/projects/v2kparse

✭ 44

java ANTLR ruby GAP SystemVerilog Verilog

215. sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

✭ 45

Verilog SystemVerilog tcl python Stata fpga controller dram quartus sdram as4c4m16sa

216. Curso-Electronica-Digital-para-makers-con-FPGAs-Libres

Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers

✭ 17

Verilog SystemVerilog course fpga fpgawars

217. pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog

✭ 22

c Verilog Makefile Inno Setup verification verilog virtual modelling cosim pcie pli bfm

218. stereo-vision-fpga

Real-time binocular stereo vision FPGA system with OV5640 cameras

✭ 20

tcl VHDL C++Verilog c objective c SystemVerilog fpga stereo-vision vivado-hls

219. lighthouse-fpga

No description, website, or topics provided.

✭ 18

scala Verilog python

220. UPDuino-LH154Q01-Display

Design to connect Lattice Ultraplus FPGA to LH154Q01 Display

✭ 24

c Verilog C++

221. verilator

A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.

✭ 17

C++Verilog perl c

222. FPGA NTP SERVER

A FPGA implementation of the NTP and NTS protocols

✭ 27

Verilog python c Makefile tcl shell SystemVerilog fpga verilog fpga-ntp-server

223. introduction-to-fpga

No description, website, or topics provided.

✭ 60

Verilog c Makefile

224. mips32r1 core

A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.

✭ 13

Verilog

225. mksocfpga

Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx

✭ 23

VHDL tcl SystemVerilog Makefile Verilog shell zynq fpga-platforms

226. NES on FPGA

implemented NES on an FPGA.

✭ 27

c Verilog VHDL

227. sancus-core

Minimal OpenMSP430 hardware extensions for isolation and attestation

✭ 17

Verilog tcl VHDL c shell OpenEdge ABL

228. openarty

An Open Source configuration of the Arty platform

✭ 93

Verilog C++Coq c Makefile shell fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

229. amber samples

No description, website, or topics provided.

✭ 17

Verilog c assembly C++shell

230. eddr3

mirror of https://git.elphel.com/Elphel/eddr3

✭ 33

Verilog SystemVerilog python HCL fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

231. fpgaboy

Implementation Nintendo's GameBoy console on an FPGA

✭ 83

Verilog python

232. Nu6509

Emulate a 6509 with a 6502

✭ 16

Verilog

233. Lattuino IP Core

An Arduino UNO compatible implementation for the iCE40 FPGAs

✭ 16

C++c VHDL Verilog Makefile perl

234. salent

A toy x86 disassembler and x86 style toy chip

✭ 16

assembly perl c VHDL Verilog

235. oc jpegencode

Fork of OpenCores jpegencode with Cocotb testbench

✭ 38

Verilog Coq

236. MIPS-architecture-CPU-design-based-on-FPGA

基于FPGA的MIPS架构的CPU设计

✭ 23

c HTML Verilog shell VHDL tcl

237. Vortex

RISC-V GPGPU

✭ 32

C++Verilog c assembly Makefile shell Coq

238. dana

Dana - a purely functional (virtual) operating system

✭ 16

haskell c Verilog

239. R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

✭ 70

Verilog c cpu tiny verilog 8bit

240. buffets

Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

✭ 30

Verilog

241. ThymesisFlow

Memory Disaggregation on POWER9 with OpenCAPI 3.0 M1 & C1

✭ 26

Verilog V c C++tcl Makefile

242. eco32

32-Bit RISC microprocessor system for FPGA boards

✭ 32

c Verilog Roff assembly Makefile HTML

243. CNNIOT

No description, website, or topics provided.

✭ 29

LLVM C++Ada VHDL Verilog tcl

244. opc

One Page CPU Project - CPU, Assembler & Emulator each in a single page of code

✭ 69

assembly Limbo python Verilog Brainfuck perl

245. dac sdc 2020

DAC System Design Contest 2020

✭ 29

tcl Jupyter Notebook python Verilog shell Makefile

246. Basys3

XUP Basys3 Boards' LIBs and Projects

✭ 23

tcl Verilog Coq

247. Arcade-Galaga MiSTer

Arcade: Galaga for MiSTer

✭ 12

VHDL Verilog SystemVerilog tcl Batchfile

248. OpenIRV

Open-source thermal camera project

✭ 29

Verilog tcl

249. icehat

No description, website, or topics provided.

✭ 28

KiCad Layout c Verilog

250. tinyfpga bx usbserial

USB Serial on the TinyFPGA BX

✭ 108

Verilog Makefile

201-250 of 626 Verilog projects