398 Open source projects that are alternatives of or similar to conifer

A simple and efficient single producer multiple consumer queue, suititable for both ITC and IPC.

A low cost FPGA development board for absolute newbies

A scalable High-Level Synthesis framework on MLIR

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

A collection of non-blocking(polling) network libs for Linux, also support solarflare APIs(Tcpdirect/Efvi)

Video Game custom chips reverse-engineered from silicon

Spector: An OpenCL FPGA Benchmark Suite

Clio, ASPLOS'22.

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

mirror of https://git.elphel.com/Elphel/eddr3

A revised version of NanoLog which writes human readable log file, and is easier to use.

🎤 Reliable low-latency audio playback and recording with Python 🐍

Homebrew game for homebrew FPGA game console

This repository contains synthesizable examples which use the PoC-Library.

FPGA CryptoNight V7 Minner

Antmicro's fast, vendor-neutral DMA IP in Chisel

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Performance comparison of the most popular C++ serialization protocols such as Cap'n'Proto, FastBinaryEncoding, Flatbuffers, Protobuf, JSON

EVEREST: e-Versatile Research Stick for peoples

A FPGA core for the arcade game, Rygar (1986).

A FPGA implementation of the NTP and NTS protocols

RISCV SoftCPU Contest 2018

zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。

Web-based HDL diagramming tool

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

PhyWhisperer-USB: Hardware USB Trigger

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Wishbone controlled I2C controllers

Global Dark Mode for ALL apps on ANY platforms.

Lighter-than-air, peer-to-peer, bounded, non-blocking, non-threaded, etc., publish-subscribe networking

The project is the official implementation of our CVPR 2021 paper, "Restoring Extremely Dark Images in Real Time"

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A configurable C++ generator of pipelined Verilog FFT cores

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

Asynchronous Audio / Video Library for H264 / MJPEG / OPUS / AAC / MP2 encoding, transcoding, recording and streaming from live sources

Generate UVM register model from compiled SystemRDL input

🌟 Alhambra II FPGA board

PYNQ Composabe Overlays

HW Design: A Functional Approach

Project F brings FPGAs to life with exciting open-source designs you can build on.

A JSON library implemented in VHDL.

A collection of phase locked loop (PLL) related projects

A full-speed device-side USB peripheral core written in Verilog.

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Common elements for FPGA Design (FIFOs, RAMs, etc.)

Real-time binocular stereo vision FPGA system with OV5640 cameras

List of ideas for getting started with TimVideos projects

An Open Source configuration of the Arty platform

Robotic Application Processor

Project X-Ray Database: XC7 Series

An example of how to use the Xilinx ISE toolchain from the command line

Library of approximate arithmetic circuits

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

DFiant: A Dataflow Hardware Descripition Language

DDC/DUC SDR Tranceiver project