574 Open source projects that are alternatives of or similar to Cores Swerv El2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SweRV EH1 core

FPGA-based RISC-V CPU+SoC.

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Yet Another RISC-V Implementation

RISC-V processor emulator written in Rust+WASM

ARV: Asynchronous RISC-V Go High-level Functional Model

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Quasar 2.0: Chisel equivalent of SweRV-EL2

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

SystemOT, yet another home brew cpu.

SpinalHDL - Cryptography libraries

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Yet another toy CPU.

Nuclei RISC-V Software Development Kit

A RISC-V simulator

FPGA 101 - Workshop materials

Code generation tool for configuration and status registers

EVEREST: e-Versatile Research Stick for peoples

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Homebrew game for homebrew FPGA game console

RISCV SoftCPU Contest 2018

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

A simple three-stage RISC-V CPU

Sphinx Extension which generates various types of diagrams from Verilog code.

SoC based on VexRiscv and ICE40 UP5K

FPGA-based JPEG-LS image compressor.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

Sedna - a pure Java RISC-V emulator.

Virtio implementation in SystemVerilog

MDEPX — A BSD-style RTOS

RISC-V RV32I[MAC] emulator with ELF support

Simple risc-v emulator, able to run linux, written in C.

Imitate SDcard using FPGAs.

⛔ DEPRECATED ⛔ HERO Software Development Kit

List of ideas for getting started with TimVideos projects

RISC-V Cores, SoC platforms and SoCs

Various HDL (Verilog) IP Cores

Maxine VM: A meta-circular research VM

Nuclei Microcontroller Software Interface Standard Development Repo

Haskell library for hardware description

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

A self-hosting and educational C compiler

The OpenPiton Platform

RISC-V CPU Core (RV32IM)

Repository for basic (and not so basic) Verilog blocks with high re-use potential

RISC-V Assembler and Runtime Simulator

SonicBOOM: The Berkeley Out-of-Order Machine

RARS -- RISC-V Assembler and Runtime Simulator

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

RISC-V Cores, SoC platforms and SoCs

A FPGA friendly 32 bit RISC-V CPU implementation

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

No-MMU Linux capable RISC-V SoC designed to be useful.

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz