551 Open source projects that are alternatives of or similar to eddr3

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Global Dark Mode for ALL apps on ANY platforms.

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Virtio implementation in SystemVerilog

DMA source and sink blocks for Xilinx Zynq FPGAs

Tools for running FPGA vendor toolchains with Docker

SHA-256 IP core for ZedBoard (Zynq SoC)

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Recipe for FPGA cooking

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Notes on the Red Pitaya Open Source Instrument

Bus bridges and other odds and ends

32-bit Superscalar RISC-V CPU

Must-have verilog systemverilog modules

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Yet Another RISC-V Implementation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

📡 Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz

NN on FPGA

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

Programmable multichannel ADPCM decoder for FPGA

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

CHIP-8 console on FPGA

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

FPGA/hardware design of openwifi

CNN acceleration on virtex-7 FPGA with verilog HDL

All open source file and project for OpenFPGAduino project

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Docker Development Environment for SpinalHDL

Simple, zero-copy DMA to/from userspace.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Sphinx Extension which generates various types of diagrams from Verilog code.

A programming language for FPGAs.

Cross EDA Abstraction and Automation

Lattice iCE40: development platform for PlatformIO

Yet Another Tetris on FPGA Implementation

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

MOS6581 SID chip emulator in SystemVerilog

Small Processing Unit 32: A compact RV32I CPU written in Verilog

SpinalHDL - Cryptography libraries

Generator of verilog description for FPGA MobileNet implementation

Dockerfile with Vivado for CI

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA-based JPEG-LS image compressor.

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

PDP-6 Emulator

A simple, basic, formally verified UART controller

LicheeTang 蜂鸟E203 Core

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.