690 Open source projects that are alternatives of or similar to Embedded Neural Network

HW Design: A Functional Approach

RISC-V Cores, SoC platforms and SoCs

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

DFiant: A Dataflow Hardware Descripition Language

A curated list of awesome open source hardware design tools

Various HDL (Verilog) IP Cores

Import and export IP-XACT XML register models

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemRDL 2.0 language compiler front-end

32-bit Superscalar RISC-V CPU

FPGA CryptoNight V7 Minner

VUnit is a unit testing framework for VHDL/SystemVerilog

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Generate UVM register model from compiled SystemRDL input

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Video Game custom chips reverse-engineered from silicon

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Code generation tool for configuration and status registers

Haskell to VHDL/Verilog/SystemVerilog compiler

RISC-V Cores, SoC platforms and SoCs

An experiment for building gateware for the axiom micro / beta using nmigen and yosys

RISC-V CPU Core (RV32IM)

Lossless data compression in Go

Draco is a library for compressing and decompressing 3D geometric meshes and point clouds. It is intended to improve the storage and transmission of 3D graphics.

Brevitas: quantization-aware training in PyTorch

Writing large ZIP archives without memory inflation

A simple integer compression library in Java

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

JNI binding for Zstd

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

mango fun framework

Building better compression together

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Data compression in TensorFlow

Transfer 10Gbps http traffic over 1Gbps networks :)

Caffe for Sparse and Low-rank Deep Neural Networks

中文版 Parallel Programming for FPGAs

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Minify size your images. Image compression with extension: jpg/jpeg, svg, png, gif. NodeJs

AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.

Digital Signature Service : creation, extension and validation of advanced electronic signatures

A simple C library for compressing lists of integers using binary packing

Pure golang package for reading and writing xz-compressed files

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

An open source library for image processing on FPGA.

lzbench is an in-memory benchmark of open-source LZ77/LZSS/LZMA compressors

Web-based ZooKeeper UI / editor / browser

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

A Just-In-Time Compiler for Verilog from VMware Research

SDAccel Examples

Collection of compression related Go packages.

Lizard (formerly LZ5) is an efficient compressor with very fast decompression. It achieves compression ratio that is comparable to zip/zlib and zstd/brotli (at low and medium compression levels) at decompression speed of 1000 MB/s and faster.

Android multi-media selector based on MVP mode.

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

A user interface for Windows 10 filesystem compression

SweRV EH1 core

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.