PoC-ExamplesThis repository contains synthesizable examples which use the PoC-Library.
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noasicAn open-source VHDL library for FPGA design.
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Dsi ShieldArduino MIPI DSI Shield
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CryptoHDLA list of VHDL codes implementing cryptographic algorithms
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SpinalCryptoSpinalHDL - Cryptography libraries
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Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
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JSON-for-VHDLA JSON library implemented in VHDL.
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SpinalhdlScala based HDL
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OpenNASOpenN@S: Open-source software to NAS automatic VHDL code generation
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Opl3 fpgaReverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
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vcdVCD file (Value Change Dump) command line viewer
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verilog-vcd-parserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
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mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
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fphdlVHDL-2008 Support Library
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NvcVHDL compiler and simulator
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symbolatorHDL symbol generator
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I2s Interface VhdlA simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
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yavhdlYet Another VHDL tool
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EdalizeAn abstraction library for interfacing EDA tools
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vboardVirtual development board for HDL design
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VunitVUnit is a unit testing framework for VHDL/SystemVerilog
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vhdl-hdmi-outHDMI Out VHDL code for 7-series Xilinx FPGAs
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SmartVHDLSublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)
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fpga puf🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
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xedaCross EDA Abstraction and Automation
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Awesome HdlHardware Description Languages
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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getting-startedList of ideas for getting started with TimVideos projects
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MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
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QNICE-FPGAQNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
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pyarch🔌 Hardware Abstraction Library in Python
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Mist BoardCore sources and tools for the MIST board
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cocotb-busPre-packaged testbenching tools and reusable bus interfaces for cocotb
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Cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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pyVHDLParserStreaming based VHDL parser.
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F32cA 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
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mrisc32-a1A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
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formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
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HalHAL – The Hardware Analyzer
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vim-hdlVim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
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GplgpuGPL v3 2D/3D graphics engine in verilog
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Csi2rxOpen Source 4k CSI-2 Rx core for Xilinx FPGAs
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CacheSimple implementation of cache using VHDL
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SiaFpgaMinerVHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin
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simple-riscvA simple three-stage RISC-V CPU
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BenEaterVHDLVHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
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Parallella HwParallella board design files
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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
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Zedboard audioA Audio Interface for the Zedboard
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Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
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GcvideoGameCube Digital AV converter
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dockerScripts to build and use docker images including GHDL
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