824 Open source projects that are alternatives of or similar to FPGA-USB-Device

Various HDL (Verilog) IP Cores

Sphinx Extension which generates various types of diagrams from Verilog code.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Docker Development Environment for SpinalHDL

Scala based HDL

Virtio implementation in SystemVerilog

List of ideas for getting started with TimVideos projects

Imitate SDcard using FPGAs.

FPGA-based JPEG-LS image compressor.

An open source cross-platform USB stack for embedded system

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Code generation tool for configuration and status registers

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A full-speed device-side USB peripheral core written in Verilog.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

SpinalHDL - Cryptography libraries

Haskell library for hardware description

FPGA-based RISC-V CPU+SoC.

Recipe for FPGA cooking

Yet Another Tetris on FPGA Implementation

Cross EDA Abstraction and Automation

A programming language for FPGAs.

Lattice iCE40: development platform for PlatformIO

Programmable multichannel ADPCM decoder for FPGA

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Tiny and portable USB device/host stack for embedded system with USB IP

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Small Processing Unit 32: A compact RV32I CPU written in Verilog

i2c to usb hid multi touch with stm32

Facilitates building open source tools for working with hardware description languages (HDLs)

A configurable C++ generator of pipelined Verilog FFT cores

MOS6581 SID chip emulator in SystemVerilog

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

A Hardware Construct Language

Curated list of resources relating to the WebHID (Human Interface Device) API

Generator of verilog description for FPGA MobileNet implementation

NN on FPGA

PDP-6 Emulator

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

USB Composite Device Demo (Keyboard, Custom HID and Massive Storage) using CH55x

Yet Another RISC-V Implementation

QT Py Media Knob using rotary encoder & neopixel ring

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Linux driver to properly initialize some Thrustmaster Wheels

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Drop In USB CDC ACM core for iCE40 FPGA

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Python library to control Chinese USB HID 125Khz RFID Reader/Writer

A Rust library to run a USB/IP server

A FPGA implementation of the NTP and NTS protocols