342 Open source projects that are alternatives of or similar to Kryon

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Dreamcast HDMI

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Connectal is a framework for software-driven hardware development.

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

SystemVerilog compiler and language services

An FPGA based GDROM emulator for the Sega Dreamcast

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

SystemVerilog language server

A Video display simulator

All open source file and project for OpenFPGAduino project

i8080 precise replica in Verilog, based on reverse engineering of real die

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

LicheeTang 蜂鸟E203 Core

Open source software for chip reverse engineering.

浙江大学计算机体系结构课程实验

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

SystemVerilog linter

Chisel 3: A Modern Hardware Design Language

GPGPU microprocessor architecture

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

iCESugar FPGA Board (base on iCE40UP5k)

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Verilog version of Z-scale (deprecated)

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Core description files for FuseSoC

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

Test suite designed to check compliance with the SystemVerilog standard.

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

A utility for Composing FPGA designs from Peripherals

Repository for the SCALE-MAMBA MPC system

RePlAce global placement tool

A simple, basic, formally verified UART controller

A convolutional neural network implemented in hardware (verilog)

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Repurposing existing HDL tools to help writing better code

🌱 ❄️ Collection of open-source peripherals in Verilog

Verilog module for calculation of FFT.

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

A List of Free and Open Source Hardware Verification Tools and Frameworks

All code found on nandland is here. underconstruction.gif

A 32-bit Microcontroller featuring a RISC-V core

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Pano Logic G2 Reverse Engineering Project

PicoRV32 - A Size-Optimized RISC-V CPU

Light-weight RISC-V RV32IMC microcontroller core.

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

A Verilog implementation of DisplayPort protocol for FPGAs

Recipe for FPGA cooking

Hardware implementation of the SHA-256 cryptographic hash function

SystemVerilog to Verilog conversion

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

NES in Verilog