518 Open source projects that are alternatives of or similar to Openlane

mirror of https://git.elphel.com/Elphel/eddr3

A configurable C++ generator of pipelined Verilog FFT cores

Ruby interface to IEEE 1364-2005 Verilog VPI

A collection of phase locked loop (PLL) related projects

A right-to-left theme for Jekyll with Jalali support and some other goodies.

Project Oberon (New Edition 2013) Unofficial Mirror

A homekit firmware for a magic home RGBW controller

Rust high level bindings crate for the `libmagic` C library

HDL symbol generator

RTL version of materializecss framework v1.0.0

DFiant: A Dataflow Hardware Descripition Language

The OpenPiton Platform

FPGA CryptoNight V7 Minner

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Nim cell magic for JupyterLab or Juypter Python Notebooks.

A collection of (more or less) useful traits for PHP7.2+

A full-speed device-side USB peripheral core written in Verilog.

Quasar 2.0: Chisel equivalent of SweRV-EL2

OOUI is a modern JavaScript UI library with strong cross-browser support. It is the standard library for MediaWiki and Wikipedia. This is a mirror from https://gerrit.wikimedia.org. Main website:

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

A FPGA implementation of the NTP and NTS protocols

Laravel localization package for wrapping routes in multiple locale prefixes

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

No description or website provided.

Simple interface to libmagic for Ruby Programming Language

Verilog (SystemVerilog) coding style

ZX Spectrum CPLD-based clone for rubber case

Dark magic delights in Python

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

NetFPGA 1G infrastructure and gateware

An abstraction library for interfacing EDA tools

Deck Tracker for Magic Arena [DEPRECATED]

Generate UVM register model from compiled SystemRDL input

Bazel build rules for Verilator

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

Repository gathering basic modules for CDC purpose

Enlite Starter - React Dashboard Starter Template with Firebase Auth

Nozha is a rtl / ltr Admin Panel with Dark Mode

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

This repository contains public source files for use in SER334 (Operating Systems & Networks) at Arizona State University.

Revengineered ancient PDP-11 CPUs, originals and clones

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

MTGJSON build scripts to generate alternative data formats

A collection of magic animations for react components.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

HDLBits website practices & solutions

A Single Page Application to help zeldaPlay players to track their characters and progress

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

An assistant to guess your pip dependencies from your code, without using a requirements file.

If you are looking for a stylish and elegant website template for your online store, Hypermarket is the perfect choice for you.

Import and export IP-XACT XML register models

List of ideas for getting started with TimVideos projects

Reads a state transition system and performs property checking

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board