VgasimA Video display simulator
Stars: ✭ 94 (-30.37%)
Oldland CpuOldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Stars: ✭ 90 (-33.33%)
Spatial LangSpatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
Stars: ✭ 99 (-26.67%)
C65gsFPGA-based C64 Accelerator / C65 like computer
Stars: ✭ 79 (-41.48%)
Raven Picorv32Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Stars: ✭ 110 (-18.52%)
FpganesNES in Verilog
Stars: ✭ 119 (-11.85%)
VsdflowVSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Stars: ✭ 82 (-39.26%)
SvlintSystemVerilog linter
Stars: ✭ 103 (-23.7%)
AntikernelThe Antikernel operating system project
Stars: ✭ 75 (-44.44%)
Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
Stars: ✭ 114 (-15.56%)
NyuziprocessorGPGPU microprocessor architecture
Stars: ✭ 1,351 (+900.74%)
Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
Stars: ✭ 126 (-6.67%)
LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Stars: ✭ 110 (-18.52%)
Lpc sniffer tpmA low pin count sniffer for ICEStick - targeting TPM chips
Stars: ✭ 91 (-32.59%)
Fpga based cnnFPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
Stars: ✭ 129 (-4.44%)
Wujian100 openIC design and development should be faster,simpler and more reliable
Stars: ✭ 1,252 (+827.41%)
A2o Stars: ✭ 107 (-20.74%)
CpuA very primitive but hopefully self-educational CPU in Verilog
Stars: ✭ 80 (-40.74%)
SvlsSystemVerilog language server
Stars: ✭ 119 (-11.85%)
Ustc RvsocFPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-42.96%)
Archexp浙江大学计算机体系结构课程实验
Stars: ✭ 104 (-22.96%)
VscaleVerilog version of Z-scale (deprecated)
Stars: ✭ 116 (-14.07%)
MriscvA 32-bit Microcontroller featuring a RISC-V core
Stars: ✭ 101 (-25.19%)
Picorv32PicoRV32 - A Size-Optimized RISC-V CPU
Stars: ✭ 1,856 (+1274.81%)
Panologic G2Pano Logic G2 Reverse Engineering Project
Stars: ✭ 99 (-26.67%)
Orpsoc CoresCore description files for FuseSoC
Stars: ✭ 112 (-17.04%)
KamikazeLight-weight RISC-V RV32IMC microcontroller core.
Stars: ✭ 94 (-30.37%)
Fpga Peripherals🌱 ❄️ Collection of open-source peripherals in Verilog
Stars: ✭ 130 (-3.7%)
Mips32 Cpu奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)
Stars: ✭ 94 (-30.37%)
Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
Stars: ✭ 108 (-20%)
Displayport verilogA Verilog implementation of DisplayPort protocol for FPGAs
Stars: ✭ 125 (-7.41%)
Fpga CnnFPGA implementation of Cellular Neural Network (CNN)
Stars: ✭ 91 (-32.59%)
AutofpgaA utility for Composing FPGA designs from Peripherals
Stars: ✭ 108 (-20%)
IvtestRegression test suite for Icarus Verilog.
Stars: ✭ 90 (-33.33%)
Wbuart32A simple, basic, formally verified UART controller
Stars: ✭ 133 (-1.48%)
HoodlumA nicer HDL.
Stars: ✭ 88 (-34.81%)
ReplaceRePlAce global placement tool
Stars: ✭ 109 (-19.26%)
PonylinkA single-wire bi-directional chip-to-chip interface for FPGAs
Stars: ✭ 80 (-40.74%)
Hardware CnnA convolutional neural network implemented in hardware (verilog)
Stars: ✭ 107 (-20.74%)
HomotopyHomotopy theory in Coq.
Stars: ✭ 79 (-41.48%)
NandlandAll code found on nandland is here. underconstruction.gif
Stars: ✭ 128 (-5.19%)
TooobaRISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Stars: ✭ 79 (-41.48%)
Hdl checkerRepurposing existing HDL tools to help writing better code
Stars: ✭ 103 (-23.7%)
SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
Stars: ✭ 116 (-14.07%)
Fft Dit FpgaVerilog module for calculation of FFT.
Stars: ✭ 104 (-22.96%)
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (-2.96%)
MilkymistSoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
Stars: ✭ 127 (-5.93%)
ConnectalConnectal is a framework for software-driven hardware development.
Stars: ✭ 117 (-13.33%)
IcegdromAn FPGA based GDROM emulator for the Sega Dreamcast
Stars: ✭ 103 (-23.7%)