494 Open source projects that are alternatives of or similar to Openroad

Code generation tool for configuration and status registers

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Chisel Things for OFDM

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Test suite designed to check compliance with the SystemVerilog standard.

Various HDL (Verilog) IP Cores

Chisel 3: A Modern Hardware Design Language

Imitate SDcard using FPGAs.

A Hardware Construct Language

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A High-performance Timing Analysis Tool for VLSI Systems

Repository for basic (and not so basic) Verilog blocks with high re-use potential

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Virtio implementation in SystemVerilog

Facilitates building open source tools for working with hardware description languages (HDLs)

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Docker Development Environment for SpinalHDL

Test suite designed to check compliance with the SystemVerilog standard.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Recipe for FPGA cooking

Sphinx Extension which generates various types of diagrams from Verilog code.

SpinalHDL - Cryptography libraries

Haskell library for hardware description

FPGA-based JPEG-LS image compressor.

Cross EDA Abstraction and Automation

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

FPGA-based RISC-V CPU+SoC.

Scala based HDL

An abstraction library for interfacing EDA tools

WAL enables programmable waveform analysis.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

OlliePy is a python package which can help data scientists in exploring their data and evaluating and analysing their machine learning experiments by utilising the power and structure of modern web applications. The data scientist only needs to provide the data and any required information and OlliePy will generate the rest.

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

2019 CCF

Global Dark Mode for ALL apps on ANY platforms.

odio is now Strimio!

Quasar 2.0: Chisel equivalent of SweRV-EL2

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes

A list of software and papers related to automatic and fast Exploratory Data Analysis

Verilog PCI express components

ZX Spectrum CPLD-based clone for rubber case

Generate UVM register model from compiled SystemRDL input

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

VLSI EDA Global Router

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

List of ideas for getting started with TimVideos projects

Efficient implementations of the transcendental functions

Homebrew game for homebrew FPGA game console

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

data⎰describe: Pythonic EDA Accelerator for Data Science

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)