922 Open source projects that are alternatives of or similar to sphinxcontrib-hdl-diagrams

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Wishbone controlled I2C controllers

Global Dark Mode for ALL apps on ANY platforms.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A configurable C++ generator of pipelined Verilog FFT cores

A MIPS CPU implemented in Verilog

Homebrew game for homebrew FPGA game console

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Human Resource Machine - CPU Design #HRM

A mixed signal netlist language (pre-alpha)

A FPGA friendly 32 bit RISC-V CPU implementation

FPGA 101 - Workshop materials

High throughput JPEG decoder in Verilog for FPGA

The Antikernel operating system project

The OpenPiton Platform

SweRV EL2 Core

Compact FPGA game console

A Just-In-Time Compiler for Verilog from VMware Research

SweRV EH1 core

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

A small, light weight, RISC CPU soft core

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

A utility for Composing FPGA designs from Peripherals

The USRP™ Hardware Driver Repository

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

A programming language for FPGAs.

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

A full-speed device-side USB peripheral core written in Verilog.

A reimplementation of a tiny stack CPU

A Video display simulator

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Automatic links from code examples to reference documentation

Tools for running FPGA vendor toolchains with Docker

This is a higan/Verilator co-simulation example/framework

A wishbone controlled scope for FPGA's

Image Processing Toolbox in Verilog using Basys3 FPGA

Must-have verilog systemverilog modules

Example designs showing different ways to use SymbiFlow toolchains.

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

32-bit Superscalar RISC-V CPU

CNN acceleration on virtex-7 FPGA with verilog HDL

GPGPU microprocessor architecture

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Haskell to VHDL/Verilog/SystemVerilog compiler

A simple, basic, formally verified UART controller

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Notes on the Red Pitaya Open Source Instrument

LicheeTang 蜂鸟E203 Core

Yet Another Tetris on FPGA Implementation

Verilog Generator of Neural Net Digit Detector for FPGA

Connectal is a framework for software-driven hardware development.

All open source file and project for OpenFPGAduino project

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

FPGA/hardware design of openwifi

Bus bridges and other odds and ends

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

mirror of https://git.elphel.com/Elphel/eddr3