vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (-64.44%)
Platformio Vscode IdePlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Stars: ✭ 676 (+400.74%)
ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
Stars: ✭ 18 (-86.67%)
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Stars: ✭ 83 (-38.52%)
kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Stars: ✭ 167 (+23.7%)
SpinalhdlScala based HDL
Stars: ✭ 696 (+415.56%)
ZbasicA bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Stars: ✭ 27 (-80%)
LVDS-7-to-1-SerializerAn Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
Stars: ✭ 33 (-75.56%)
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (-71.85%)
SpinalCryptoSpinalHDL - Cryptography libraries
Stars: ✭ 36 (-73.33%)
MobileNet-in-FPGAGenerator of verilog description for FPGA MobileNet implementation
Stars: ✭ 107 (-20.74%)
fpga-nnNN on FPGA
Stars: ✭ 16 (-88.15%)
picorv32 XilinxA picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
Stars: ✭ 49 (-63.7%)
EDSACFPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
Stars: ✭ 28 (-79.26%)
AntikernelThe Antikernel operating system project
Stars: ✭ 75 (-44.44%)
KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Stars: ✭ 37 (-72.59%)
FPGA NTP SERVERA FPGA implementation of the NTP and NTS protocols
Stars: ✭ 27 (-80%)
eddr3mirror of https://git.elphel.com/Elphel/eddr3
Stars: ✭ 33 (-75.56%)
wbi2cWishbone controlled I2C controllers
Stars: ✭ 25 (-81.48%)
Symbiflow ExamplesExample designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-47.41%)
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (+7.41%)
RiscboyPortable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Stars: ✭ 103 (-23.7%)
Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-77.04%)
J1scA reimplementation of a tiny stack CPU
Stars: ✭ 64 (-52.59%)
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
Stars: ✭ 29 (-78.52%)
SpinalDevDocker Development Environment for SpinalHDL
Stars: ✭ 17 (-87.41%)
IrohaIntermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Stars: ✭ 30 (-77.78%)
Higan VerilogThis is a higan/Verilator co-simulation example/framework
Stars: ✭ 35 (-74.07%)
VgasimA Video display simulator
Stars: ✭ 94 (-30.37%)
blarneyHaskell library for hardware description
Stars: ✭ 81 (-40%)
simple-riscvA simple three-stage RISC-V CPU
Stars: ✭ 14 (-89.63%)
CoresVarious HDL (Verilog) IP Cores
Stars: ✭ 271 (+100.74%)
intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Stars: ✭ 43 (-68.15%)
OpenpitonThe OpenPiton Platform
Stars: ✭ 282 (+108.89%)
Icezum🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
Stars: ✭ 280 (+107.41%)
Speech256An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
Stars: ✭ 51 (-62.22%)
Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Stars: ✭ 393 (+191.11%)
Apio🌱 Open source ecosystem for open FPGA boards
Stars: ✭ 366 (+171.11%)
NyuziprocessorGPGPU microprocessor architecture
Stars: ✭ 1,351 (+900.74%)
FiresimFireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
Stars: ✭ 415 (+207.41%)
Rsyocto🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Stars: ✭ 41 (-69.63%)
ZipcpuA small, light weight, RISC CPU soft core
Stars: ✭ 640 (+374.07%)
FwriscFeatherweight RISC-V implementation
Stars: ✭ 39 (-71.11%)
Wbuart32A simple, basic, formally verified UART controller
Stars: ✭ 133 (-1.48%)
HdlHDL libraries and projects
Stars: ✭ 727 (+438.52%)
UhdThe USRP™ Hardware Driver Repository
Stars: ✭ 544 (+302.96%)
Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+609.63%)
Icestudio❄️ Visual editor for open FPGA boards
Stars: ✭ 958 (+609.63%)
Hrm CpuHuman Resource Machine - CPU Design #HRM
Stars: ✭ 43 (-68.15%)
Platformio Atom IdePlatformIO IDE for Atom: The next generation integrated development environment for IoT
Stars: ✭ 475 (+251.85%)
Basic verilogMust-have verilog systemverilog modules
Stars: ✭ 247 (+82.96%)
fpga-dockerTools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (-60%)
VGChipsVideo Game custom chips reverse-engineered from silicon
Stars: ✭ 86 (-36.3%)
Mips CpuA MIPS CPU implemented in Verilog
Stars: ✭ 38 (-71.85%)
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (-2.96%)