intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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fpga-dockerTools for running FPGA vendor toolchains with Docker
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JSON-for-VHDLA JSON library implemented in VHDL.
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J1scA reimplementation of a tiny stack CPU
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
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Deep-DarkFantasyGlobal Dark Mode for ALL apps on ANY platforms.
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cocotb-busPre-packaged testbenching tools and reusable bus interfaces for cocotb
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mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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SpinalhdlScala based HDL
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AleCheck syntax in Vim asynchronously and fix files, with Language Server Protocol (LSP) support
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dockerScripts to build and use docker images including GHDL
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EdalizeAn abstraction library for interfacing EDA tools
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TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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ixo-usb-jtagusb-jtag - Altera USB Blaster Emulation with a FX2
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symbolatorHDL symbol generator
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xedaCross EDA Abstraction and Automation
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MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
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Awesome HdlHardware Description Languages
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Cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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OphidianOphidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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SpinalDevDocker Development Environment for SpinalHDL
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vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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verilog-vcd-parserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
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eddr3mirror of https://git.elphel.com/Elphel/eddr3
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DegateOpen source software for chip reverse engineering.
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vboardVirtual development board for HDL design
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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Hdl checkerRepurposing existing HDL tools to help writing better code
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virtioVirtio implementation in SystemVerilog
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SpinalCryptoSpinalHDL - Cryptography libraries
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meta-gitgit plugin for meta
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tabToWindowChrome extension to move the current tab to a new window using the command API
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autoscreenAutomated screen capture utility
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fpga-nnNN on FPGA
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indicesIndices creates a Table of Contents sidebar for Medium articles, and enables you to skip around
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screenRECA really simple , ad-free & minimal web based screen recorder 📹
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nv-ideNeovim custom configuration, oriented for full stack developers (rails, ruby, php, html, css, SCSS, javascript)
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vericertA formally verified high-level synthesis tool based on CompCert and written in Coq.
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MagicBoxOrganize your workspace, keep files optimized, prepare images for publishing
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pdp6PDP-6 Emulator
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Verilog-Gadget🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.
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pocketizerUnofficial Pocket new tab extension for Chrome, Firefox, and Edge
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timeleft⏳ Don't waste your time or time will waste you! ☠️ One tends to consume time on low-return stuff, superficial entertainment. 📺 Things they don't actually want to do. One should make the most of his time. ⏱ Get busy living.
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project-managementA basic CLI for regularly updating your project's status
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filestylefilestyle is a Vim plugin that highlights unwanted whitespace and characters.
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hiveql-parserHiveQL Parser. Parse HiveQL code and print AST in JSON format if success, else print well formed syntax error message.
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Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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