1058 Open source projects that are alternatives of or similar to xeda

Global Dark Mode for ALL apps on ANY platforms.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Homebrew game for homebrew FPGA game console

Open source ultrasound processing modules and building blocks

Verilog Generator of Neural Net Digit Detector for FPGA

Various HDL (Verilog) IP Cores

Notes on the Red Pitaya Open Source Instrument

Imitate SDcard using FPGAs.

Haskell library for hardware description

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

The OpenPiton Platform

FPGA/hardware design of openwifi

A simple three-stage RISC-V CPU

RISC-V CPU Core (RV32IM)

Bus bridges and other odds and ends

CHIP-8 console on FPGA

Recipe for FPGA cooking

An open source library for image processing on FPGA.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

🌱 Open source ecosystem for open FPGA boards

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

VUnit is a unit testing framework for VHDL/SystemVerilog

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

The USRP™ Hardware Driver Repository

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Generate UVM register model from compiled SystemRDL input

LicheeTang 蜂鸟E203 Core

A small, light weight, RISC CPU soft core

A simple, basic, formally verified UART controller

Package manager and build abstraction tool for FPGA/ASIC development

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

AES-128 hardware implementation

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Simple, orthogonal 32-bit computer architecture and environment

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

❄️ Visual editor for open FPGA boards

This is a higan/Verilator co-simulation example/framework

i8080 precise replica in Verilog, based on reverse engineering of real die

Human Resource Machine - CPU Design #HRM

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

A utility for Composing FPGA designs from Peripherals

A wishbone controlled scope for FPGA's

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A mixed signal netlist language (pre-alpha)

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

A MIPS CPU implemented in Verilog

SPI master and slave for FPGA written in VHDL