2794 Open source projects that are alternatives of or similar to Apio

NN on FPGA

Wishbone controlled I2C controllers

A full-speed device-side USB peripheral core written in Verilog.

MOS6581 SID chip emulator in SystemVerilog

Imitate SDcard using FPGAs.

FPGA-based JPEG-LS image compressor.

A simple SideFX Houdini package manager

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A collection of phase locked loop (PLL) related projects

Haskell library for hardware description

Virtio implementation in SystemVerilog

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Small Processing Unit 32: A compact RV32I CPU written in Verilog

SpinalHDL - Cryptography libraries

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

The package manager for Io.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Global Dark Mode for ALL apps on ANY platforms.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Video Game custom chips reverse-engineered from silicon

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

The OpenPiton Platform

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

This tool seeks to be a one-stop shop for building and working with rust- generated WebAssembly that you would like to interop with JavaScript, in the browser or with Node.js. wasm-pack helps you build rust-generated WebAssembly packages that you could publish to the npm registry, or otherwise use alongside any javascript packages in workflows that you already use, such as webpack.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Sphinx Extension which generates various types of diagrams from Verilog code.

Lattice iCE40: development platform for PlatformIO

Generator of verilog description for FPGA MobileNet implementation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

PDP-6 Emulator

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

🌎 A global Node binary manager written in Rust

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Yet Another RISC-V Implementation

A FPGA implementation of the NTP and NTS protocols

mirror of https://git.elphel.com/Elphel/eddr3

A configurable C++ generator of pipelined Verilog FFT cores

Programmable multichannel ADPCM decoder for FPGA

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Robotic Application Processor

List of ideas for getting started with TimVideos projects

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Homebrew game for homebrew FPGA game console

Aplus Command Line Tool

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

RISC-V CPU Core (RV32IM)

Various HDL (Verilog) IP Cores

Repository for basic (and not so basic) Verilog blocks with high re-use potential

An abstraction library for interfacing EDA tools

Cross EDA Abstraction and Automation

A programming language for FPGAs.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

A PHP project/micro-package generator for PDS compliant projects or micro-packages.

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

An open source library for image processing on FPGA.