609 Open source projects that are alternatives of or similar to cnn_open

Docker Development Environment for SpinalHDL

Code generation tool for configuration and status registers

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Virtio implementation in SystemVerilog

FPGA-based JPEG-LS image compressor.

FPGA-based RISC-V CPU+SoC.

Scala based HDL

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SpinalHDL - Cryptography libraries

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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Haskell library for hardware description

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A FPGA friendly 32 bit RISC-V CPU implementation

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Example designs showing different ways to use SymbiFlow toolchains.

A MIPS CPU implemented in Verilog

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Image Processing Toolbox in Verilog using Basys3 FPGA

The Antikernel operating system project

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A wishbone controlled scope for FPGA's

Haskell to VHDL/Verilog/SystemVerilog compiler

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

A reimplementation of a tiny stack CPU

FPGA 101 - Workshop materials

SweRV EL2 Core

A Video display simulator

GPGPU microprocessor architecture

High throughput JPEG decoder in Verilog for FPGA

Compact FPGA game console

Tools for running FPGA vendor toolchains with Docker

❄️ Visual editor for open FPGA boards

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Connectal is a framework for software-driven hardware development.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Must-have verilog systemverilog modules

i8080 precise replica in Verilog, based on reverse engineering of real die

A simple, basic, formally verified UART controller

LicheeTang 蜂鸟E203 Core

All open source file and project for OpenFPGAduino project

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

CNN acceleration on virtex-7 FPGA with verilog HDL

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Programmable multichannel ADPCM decoder for FPGA

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Bus bridges and other odds and ends