165 Open source projects that are alternatives of or similar to padring

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

VLSI EDA Global Router

Reverse-engineered schematics for DMG-CPU-B

SystemRDL 2.0 language compiler front-end

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Video Game custom chips reverse-engineered from silicon

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

AMC: Asynchronous Memory Compiler

Code generation tool for configuration and status registers

Import and export IP-XACT XML register models

ACT hardware description language and core tools.

Generate UVM register model from compiled SystemRDL input

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

Haskell to VHDL/Verilog/SystemVerilog compiler

HW Design: A Functional Approach

An Implementation of CAdES, XAdES, PAdES and ASiC for Windows in C++

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

RISC-V Cores, SoC platforms and SoCs

Bitcoin Stratum Pool Plugin ⛏ 📦 🔌

Mining Pools Made Easy. ⛏ 📦 🏆

Digital Signature Service : creation, extension and validation of advanced electronic signatures

A High-performance Timing Analysis Tool for VLSI Systems

A day to day plan for this challenge. Covers both theoritical and practical aspects

Are you ready to FLIRT with your wearable data?

Functionalities in Excel translated to Python

RISC-V CPU Core (RV32IM)

自动化数据探索分析和智能可视化设计应用. Automatic insights discovery and visualization for data analysis.

A microservice project using .NET Core 2.0, DDD, CQRS, Event Sourcing, Redis and RabbitMQ

Berkeley's Spatial Array Generator

Cryptocurrency ASIC mining hardware monitor using a simple web interface

Awesome ASIC design verification

Visualize and compare datasets, target values and associations, with one line of code.

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

Hive OS client for ASICs

A curated list of awesome open source hardware design tools

RISC-V Cores, SoC platforms and SoCs

VUnit is a unit testing framework for VHDL/SystemVerilog

edaviz - Python library for Exploratory Data Analysis and Visualization in Jupyter Notebook or Jupyter Lab

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

🛠️ 📊 Tools for Exploring and Comparing Data Frames

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

PCB Design Language: A programming way to design schematics.

Complete-Life-Cycle-of-a-Data-Science-Project

Various HDL (Verilog) IP Cores

Beautiful visualizations of how language differs among document types.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Rsyn – An Extensible Physical Synthesis Framework

Is there a relationship between popularity of a given technology on Stack Overflow (SO) and Hacker News (HN)? And a few words about causality

Qwertycoin is a decentralized peer-to-peer protocol for safe payments worldwide.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A powerful, innovative and intuitive EDA tool for everyone!

DFiant: A Dataflow Hardware Descripition Language

📢 Ready to learn or review your knowledge!

R package that makes basic data exploration radically simple (interactive data exploration, reproducible data science)

FPGA CryptoNight V7 Minner

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Minimum Viable Payment Terminal

Low cost Raspberry Pi /Linux based access point with audio, education and communications local content server. Inspired by the ideas of sharing with others. Anyfesto - a platform from which to speak.