Oldland CpuOldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Stars: ✭ 90 (-95.15%)
C65gsFPGA-based C64 Accelerator / C65 like computer
Stars: ✭ 79 (-95.74%)
IcegdromAn FPGA based GDROM emulator for the Sega Dreamcast
Stars: ✭ 103 (-94.45%)
Cpus CaddrFPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
Stars: ✭ 72 (-96.12%)
VsdflowVSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Stars: ✭ 82 (-95.58%)
Raven Picorv32Silicon-validated SoC implementation of the PicoSoc/PicoRV32
Stars: ✭ 110 (-94.07%)
AntikernelThe Antikernel operating system project
Stars: ✭ 75 (-95.96%)
Spatial LangSpatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
Stars: ✭ 99 (-94.67%)
Core jpegHigh throughput JPEG decoder in Verilog for FPGA
Stars: ✭ 64 (-96.55%)
A2o Stars: ✭ 107 (-94.23%)
Lpc sniffer tpmA low pin count sniffer for ICEStick - targeting TPM chips
Stars: ✭ 91 (-95.1%)
Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
Stars: ✭ 114 (-93.86%)
Wujian100 openIC design and development should be faster,simpler and more reliable
Stars: ✭ 1,252 (-32.54%)
Archexp浙江大学计算机体系结构课程实验
Stars: ✭ 104 (-94.4%)
CpuA very primitive but hopefully self-educational CPU in Verilog
Stars: ✭ 80 (-95.69%)
SvlsSystemVerilog language server
Stars: ✭ 119 (-93.59%)
Ustc RvsocFPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-95.85%)
SvlintSystemVerilog linter
Stars: ✭ 103 (-94.45%)
ComputerarchitecturelabThis repository is used to release the Labs of Computer Architecture Course from USTC
Stars: ✭ 75 (-95.96%)
LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Stars: ✭ 110 (-94.07%)
Jt gngCAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.
Stars: ✭ 65 (-96.5%)
NyuziprocessorGPGPU microprocessor architecture
Stars: ✭ 1,351 (-27.21%)
Mips32 Cpu奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)
Stars: ✭ 94 (-94.94%)
Ao68000The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
Stars: ✭ 60 (-96.77%)
ReplaceRePlAce global placement tool
Stars: ✭ 109 (-94.13%)
VscaleVerilog version of Z-scale (deprecated)
Stars: ✭ 116 (-93.75%)
Fpga CnnFPGA implementation of Cellular Neural Network (CNN)
Stars: ✭ 91 (-95.1%)
Hardware CnnA convolutional neural network implemented in hardware (verilog)
Stars: ✭ 107 (-94.23%)
IvtestRegression test suite for Icarus Verilog.
Stars: ✭ 90 (-95.15%)
HoodlumA nicer HDL.
Stars: ✭ 88 (-95.26%)
Hdl checkerRepurposing existing HDL tools to help writing better code
Stars: ✭ 103 (-94.45%)
Orpsoc CoresCore description files for FuseSoC
Stars: ✭ 112 (-93.97%)
PonylinkA single-wire bi-directional chip-to-chip interface for FPGAs
Stars: ✭ 80 (-95.69%)
Fft Dit FpgaVerilog module for calculation of FFT.
Stars: ✭ 104 (-94.4%)
HomotopyHomotopy theory in Coq.
Stars: ✭ 79 (-95.74%)
Displayport verilogA Verilog implementation of DisplayPort protocol for FPGAs
Stars: ✭ 125 (-93.27%)
TooobaRISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Stars: ✭ 79 (-95.74%)
Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
Stars: ✭ 108 (-94.18%)
MriscvA 32-bit Microcontroller featuring a RISC-V core
Stars: ✭ 101 (-94.56%)
SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
Stars: ✭ 116 (-93.75%)
Symbiflow ExamplesExample designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-96.17%)
Panologic G2Pano Logic G2 Reverse Engineering Project
Stars: ✭ 99 (-94.67%)
J1scA reimplementation of a tiny stack CPU
Stars: ✭ 64 (-96.55%)
AutofpgaA utility for Composing FPGA designs from Peripherals
Stars: ✭ 108 (-94.18%)
KamikazeLight-weight RISC-V RV32IMC microcontroller core.
Stars: ✭ 94 (-94.94%)
Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
Stars: ✭ 126 (-93.21%)
FpganesNES in Verilog
Stars: ✭ 119 (-93.59%)
ConnectalConnectal is a framework for software-driven hardware development.
Stars: ✭ 117 (-93.7%)
VgasimA Video display simulator
Stars: ✭ 94 (-94.94%)