695 Open source projects that are alternatives of or similar to Rggen

IceChips is a library of all common discrete logic devices in Verilog

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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

HDL libraries and projects

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Wishbone controlled I2C controllers

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Global Dark Mode for ALL apps on ANY platforms.

DFiant: A Dataflow Hardware Descripition Language

A configurable C++ generator of pipelined Verilog FFT cores

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Package manager and build abstraction tool for FPGA/ASIC development

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Homebrew game for homebrew FPGA game console

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Chisel Things for OFDM

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

A collection of phase locked loop (PLL) related projects

Test suite designed to check compliance with the SystemVerilog standard.

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

A full-speed device-side USB peripheral core written in Verilog.

Robotic Application Processor

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collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

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An open source library for image processing on FPGA.

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FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

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