412 Open source projects that are alternatives of or similar to Sv Tests

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Chisel 3: A Modern Hardware Design Language

Code generation tool for configuration and status registers

Facilitates building open source tools for working with hardware description languages (HDLs)

Chisel Things for OFDM

Various HDL (Verilog) IP Cores

SpinalHDL - Cryptography libraries

Test suite designed to check compliance with the SystemVerilog standard.

Virtio implementation in SystemVerilog

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

FPGA-based JPEG-LS image compressor.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Recipe for FPGA cooking

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

FPGA-based RISC-V CPU+SoC.

Docker Development Environment for SpinalHDL

Imitate SDcard using FPGAs.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A Hardware Construct Language

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Sphinx Extension which generates various types of diagrams from Verilog code.

OpenROAD's unified application implementing an RTL-to-GDS Flow

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Scala based HDL

Haskell library for hardware description

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

A 32-bit Microcontroller featuring a RISC-V core

Bitcoin miner for Xilinx FPGAs

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Dreamcast HDMI

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

A single-wire bi-directional chip-to-chip interface for FPGAs

A very primitive but hopefully self-educational CPU in Verilog

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

SweRV EL2 Core

Homotopy theory in Coq.

RePlAce global placement tool

Bootstrap RTL Standard 3 and 4

Pano Logic G2 Reverse Engineering Project

FPGA-based C64 Accelerator / C65 like computer

GPGPU microprocessor architecture

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Repurposing existing HDL tools to help writing better code

Light-weight RISC-V RV32IMC microcontroller core.

The Antikernel operating system project

Sega Genesis for MiSTer

A Video display simulator

This repository is used to release the Labs of Computer Architecture Course from USTC

A utility for Composing FPGA designs from Peripherals

浙江大学计算机体系结构课程实验

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Example designs showing different ways to use SymbiFlow toolchains.