1060 Open source projects that are alternatives of or similar to Vtr Verilog To Routing

Cross EDA Abstraction and Automation

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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

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Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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A Just-In-Time Compiler for Verilog from VMware Research

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Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

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FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

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FPGA-based JPEG-LS image compressor.

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

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mirror of https://git.elphel.com/Elphel/eddr3

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A JSON library implemented in VHDL.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

ACT hardware description language and core tools.

This repository contains synthesizable examples which use the PoC-Library.

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Generator of verilog description for FPGA MobileNet implementation

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

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CUGR, VLSI Global Routing Tool Developed by CUHK

Scripts to build and use docker images including GHDL

Homebrew game for homebrew FPGA game console

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Generate UVM register model from compiled SystemRDL input

Video Game custom chips reverse-engineered from silicon

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

Various HDL (Verilog) IP Cores

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