Top 342 verilog open source projects

CDBUS Protocol and the IP Core for FPGA users

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

This is the main repository for all the examples for the book Practical UVM

FPGA 101 - Workshop materials

Code generation tool for configuration and status registers

A mixed signal netlist language (pre-alpha)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small 6502 system with MS BASIC in ROM

A wishbone controlled scope for FPGA's

A FPGA friendly 32 bit RISC-V CPU implementation

RTL, Cmodel, and testbench for NVDLA

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)

Human Resource Machine - CPU Design #HRM

Mega CD for MiSTer

FuseSoC standard core library

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

My solutions to Alteras example labs

This is the base project for the Mojo. It should be used as the starting point for all projects.

Stuff from CTF contests

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

Featherweight RISC-V implementation

A MIPS CPU implemented in Verilog

冯爱民老师《计算机组成原理A》课程设计

CoreIR Symbolic Analyzer

Realtime VGA to ASCII Art converter

This is a higan/Verilator co-simulation example/framework

實作《自己動手寫CPU》書上的程式碼

Verilog and MIPS simple programs

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Image Processing Toolbox in Verilog using Basys3 FPGA

Haskell to VHDL/Verilog/SystemVerilog compiler

❄️ Visual editor for open FPGA boards

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

FPGA/AES/LeNet/VGG16

8MB FastRAM Board for the Amiga 500 & Amiga 500+

The 99 Traveling Salespeople Project

Barerbones OSX based Verilog simulation toolchain.

CAN Protocol Controller

CNN accelerator

Change the pitch of your voice in real-time!

FPGA-based glitcher for the Digilent Arty FPGA development board.

Galaksija computer for FPGA

Contains examples to start with Kactus2.

G.729 Encoder

collaboration on work in progress

Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.

Verilog implementation of the SHA-512 hash function.

Fixed FCT proof for latest coq and ssreflect

SDRAM controller with multiple wishbone slave ports

Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

High Speed Analog Front End FPGA Firmware for Novena PVT1

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!