Top 342 verilog open source projects

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

A Verilog implementation of DisplayPort protocol for FPGAs

NES in Verilog

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

SystemVerilog language server

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

Connectal is a framework for software-driven hardware development.

Verilog version of Z-scale (deprecated)

i8080 precise replica in Verilog, based on reverse engineering of real die

Core description files for FuseSoC

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Test suite designed to check compliance with the SystemVerilog standard.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A utility for Composing FPGA designs from Peripherals

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

RePlAce global placement tool

A convolutional neural network implemented in hardware (verilog)

Dreamcast HDMI

Repurposing existing HDL tools to help writing better code

浙江大学计算机体系结构课程实验

Verilog module for calculation of FFT.

An FPGA based GDROM emulator for the Sega Dreamcast

A List of Free and Open Source Hardware Verification Tools and Frameworks

SystemVerilog linter

A 32-bit Microcontroller featuring a RISC-V core

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

Pano Logic G2 Reverse Engineering Project

GPGPU microprocessor architecture

Light-weight RISC-V RV32IMC microcontroller core.

A Video display simulator

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Ham Radio hat for Raspberry PI

Compact FPGA game console

FuseSoC-based SoC for SweRV EH1

FPGA implementation of Cellular Neural Network (CNN)

A low pin count sniffer for ICEStick - targeting TPM chips

Regression test suite for Icarus Verilog.

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

A nicer HDL.

IC design and development should be faster，simpler and more reliable

Bitcoin miner for Xilinx FPGAs

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

A single-wire bi-directional chip-to-chip interface for FPGAs

A very primitive but hopefully self-educational CPU in Verilog

Homotopy theory in Coq.

FPGA-based C64 Accelerator / C65 like computer

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

FPGA-based RISC-V CPU+SoC.

The Antikernel operating system project

Sega Genesis for MiSTer

This repository is used to release the Labs of Computer Architecture Course from USTC

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Example designs showing different ways to use SymbiFlow toolchains.

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

A reimplementation of a tiny stack CPU

High throughput JPEG decoder in Verilog for FPGA

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.