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A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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scala shell Makefile python C++Verilog cpu processor chisel riscv rtl rt-thread verilator softcore

521. opencpi

Open Component Portability Infrastructure

✭ 54

Verilog C++VHDL c TeX shell

522. toybox

A collection of small toy programs

✭ 20

python rust lua C++c Verilog

523. tapasco

The Task Parallel System Composer (TaPaSCo)

✭ 66

Verilog tcl scala c C++rust fpga hardware hardware-acceleration fpga-soc

524. digital-servo

NIST digital servo: an FPGA based fast digital feedback controller

✭ 58

Verilog C++matlab HTML QMake c

525. FPGA-Blakecoin-Miner

An open source FPGA miner for Blakecoin

✭ 48

c python Verilog common lisp

526. the enigma project

An open source FPGA Enigma Machine created with Icestudio and Verilog

✭ 19

HTML EmberScript V python Verilog

527. 64-bit-Universal-Floating-Point-ISA-Compute-Engine

RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine

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Verilog assembly

528. Digilent-Maker

Code that goes with the Digilent Maker Space projects- to share and improve all code here is shared under the Creative Commons 3.0 License.

✭ 20

c XSLT VHDL scala javascript Verilog

529. p4fpga

P4-14/16 Bluespec Compiler

✭ 70

Bluespec C++tcl c Makefile Verilog networking prototype fpga compiler routing switch hardware-architectures p4c

530. Wolf-LITE

DUC-DDC Трансивер Wolf-Lite

✭ 21

c VHDL Verilog HTML tcl shell

531. ics-adpcm

Programmable multichannel ADPCM decoder for FPGA

✭ 18

Verilog shell audio fpga verilog adpcm

532. rtl-fuzz-lab

A Modular Open-Source Hardware Fuzzing Framework

✭ 18

SystemVerilog Verilog scala python c shell

533. ice40 examples

Public examples of ICE40 HX8K examples using Icestorm

✭ 94

Verilog Makefile

534. riscv-crypto

RISC-V cryptography extensions standardisation work.

✭ 275

c Verilog python assembly SystemVerilog Makefile shell

535. Konami arcade

No description, website, or topics provided.

✭ 20

HTML Verilog assembly CSS lua C++

536. chacha

Verilog 2001 implementation of the ChaCha stream cipher.

✭ 32

Verilog python Makefile tcl

537. fpga-booleanring-bfs

Hybrid BFS on Xilinx Zynq

✭ 18

C++Verilog scala tcl c Makefile

538. Propeller 1 Design

Propeller 1 design and example files to be run on FPGA boards.

✭ 31

Verilog SourcePawn pascal

539. StereoCensus

Verilog Implementation of the Census Transform Stereo Vision algorithm

✭ 24

Verilog python C++Makefile shell

540. riscv-soc-cores

No description, website, or topics provided.

✭ 27

Verilog tcl python c SystemVerilog shell C++

541. TRS-IO

No description, website, or topics provided.

✭ 35

GLSL HTML Verilog C++c SystemVerilog

542. icozip

A ZipCPU demonstration port for the icoboard

✭ 15

Verilog C++c Makefile objective c shell perl

543. Pepino

No description, website, or topics provided.

✭ 25

Verilog tcl VHDL Coq Batchfile python

544. VidorBitstream

No description, website, or topics provided.

✭ 58

c Verilog C++tcl shell SystemVerilog

545. Cores-SweRV fpga

No description, website, or topics provided.

✭ 31

tcl Verilog c Makefile assembly

546. Atari7800 MiSTer

Atari 7800 for MiSTer

✭ 15

Verilog SystemVerilog VHDL tcl python Batchfile

547. Coyote

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

✭ 80

SystemVerilog C++tcl c Verilog VHDL fpga tcp service amd virtualization rdma xilinx-fpga hbm

548. MIPS-Verilog

MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.

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Verilog

549. gameduino-fpga-mods

Mods of the FPGA code from @jamesbowman's Gameduino file repository

✭ 22

Verilog

550. cocotbext-eth

Ethernet interface modules for Cocotb

✭ 27

python Makefile Verilog

501-550 of 626 Verilog projects

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