SpinalDevDocker Development Environment for SpinalHDL
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vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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PoC-ExamplesThis repository contains synthesizable examples which use the PoC-Library.
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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AesAES-128 hardware implementation
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SpinalCryptoSpinalHDL - Cryptography libraries
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SpinalhdlScala based HDL
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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J1scA reimplementation of a tiny stack CPU
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Forth CpuA Forth CPU and System on a Chip, based on the J1, written in VHDL
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getting-startedList of ideas for getting started with TimVideos projects
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F32cA 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
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fpga-dockerTools for running FPGA vendor toolchains with Docker
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xedaCross EDA Abstraction and Automation
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JSON-for-VHDLA JSON library implemented in VHDL.
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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fpga puf🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
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VunitVUnit is a unit testing framework for VHDL/SystemVerilog
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EdalizeAn abstraction library for interfacing EDA tools
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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Spi FpgaSPI master and slave for FPGA written in VHDL
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Haddoc2Caffe to VHDL
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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QNICE-FPGAQNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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noasicAn open-source VHDL library for FPGA design.
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AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
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HalHAL – The Hardware Analyzer
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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captouch👇 Add capacitive touch buttons to any FPGA!
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S TuiTerminal-based CPU stress and monitoring utility
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BenEaterVHDLVHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
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Lxp32 CpuA lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
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Neo430A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
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Biriscv32-bit Superscalar RISC-V CPU
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basic-ecp5-pcbReference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
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Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
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EchomodsOpen source ultrasound processing modules and building blocks
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FPGACosmacELFA re-creation of a Cosmac ELF computer, Coded in SpinalHDL
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jagtesterExpress server load tester with middleware level data reporting
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OpenfpgaAn Open-source FPGA IP Generator
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SpoonnFPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
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hornetHornet is a simple library for stress testing
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vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
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Openwifi HwFPGA/hardware design of openwifi
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Wb2axipBus bridges and other odds and ends
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Fpga Chip8CHIP-8 console on FPGA
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HeteroclHeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
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AirPodsDesktop☄️ AirPods desktop user experience enhancement program, for Windows and Linux (WIP)
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Links-QAСборная солянка полезных ссылок для QA/тестировщика. Ссылки будут постоянно пополняться.
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