1339 Open source projects that are alternatives of or similar to getting-started

Must-have verilog systemverilog modules

A website that showcases interesting projects, using Angular JS.

EVEREST: e-Versatile Research Stick for peoples

Example designs showing different ways to use SymbiFlow toolchains.

A mixed signal netlist language (pre-alpha)

GPGPU microprocessor architecture

A Video display simulator

A simple, basic, formally verified UART controller

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

Fake News Detection Final Year College Project with Project Report, PPT, Code, Research Paper and Documents.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Connectal is a framework for software-driven hardware development.

i8080 precise replica in Verilog, based on reverse engineering of real die

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

All open source file and project for OpenFPGAduino project

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Bus bridges and other odds and ends

CHIP-8 console on FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

👇 Add capacitive touch buttons to any FPGA!

mirror of https://git.elphel.com/Elphel/eddr3

CNN acceleration on virtex-7 FPGA with verilog HDL

A programming language for FPGAs.

Programmable multichannel ADPCM decoder for FPGA

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

SPI master and slave for FPGA written in VHDL

Simple search for organisations participating/participated in the GSoC

HDL symbol generator

Yet Another Tetris on FPGA Implementation

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Lattice iCE40: development platform for PlatformIO

Wishbone controlled I2C controllers

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

RISC-V Cores, SoC platforms and SoCs

Virtio implementation in SystemVerilog

Sphinx Extension which generates various types of diagrams from Verilog code.

No-MMU Linux capable RISC-V SoC designed to be useful.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

This repository contains iCEBreaker examples for Amaranth HDL.

Simple 3-stage pipeline RISC-V processor

MOS6581 SID chip emulator in SystemVerilog

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA-based JPEG-LS image compressor.

Virtual development board for HDL design

PDP-6 Emulator

This repository contains synthesizable examples which use the PoC-Library.

Drop In USB CDC ACM core for iCE40 FPGA

NN on FPGA

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Trying to verify Verilog/VHDL designs with formal methods and tools