410 Open source projects that are alternatives of or similar to quasiSoC

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

A simple three-stage RISC-V CPU

Compact FPGA game console

RISC-V Cores, SoC platforms and SoCs

32-bit Superscalar RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

SweRV EH1 core

SweRV EL2 Core

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

List of ideas for getting started with TimVideos projects

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

RISC-V CPU Core (RV32IM)

Yet Another RISC-V Implementation

Homebrew game for homebrew FPGA game console

FPGA-based RISC-V CPU+SoC.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

RISC-V Cores, SoC platforms and SoCs

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

LicheeTang 蜂鸟E203 Core

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

🎯 soap - Structural Optimisation of Arithmetic Programs

A programming language for FPGAs.

Functional verification project for the CORE-V family of RISC-V cores.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

hBPF = eBPF in hardware

Universal Cooperative Multithread Lib with real time Scheduler that was designed to work, virtually, into any modern micro controller or Microchip and, also, for user space applications for modern OS (Mac, Linux, Windows) or on FreeRTOS as well. Supports C and C++

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

A port of FreeRTOS for the RISC-V ISA

Cross EDA Abstraction and Automation

Lattice iCE40: development platform for PlatformIO

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

This project demonstrates DSP capabilities of Terasic DE2-115

👇 Add capacitive touch buttons to any FPGA!

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Managed Machine Learning Systems and Internet of Things Live Lesson

ARMv8-A/RISC-V kernel (with UEFI bootloader)

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

The Task Parallel System Composer (TaPaSCo)

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

Fixed point package for Python.

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

RISC-V Instruction Set Metadata

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

A curated list of awesome open source hardware design tools

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Binary Neural Network on IceStick FPGA.

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Shakti: development platform for PlatformIO

Docker Development Environment for SpinalHDL

Kansas Lava implementation of MOS 6502 microprocessor

Tools for running FPGA vendor toolchains with Docker

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

shdl6800: A 6800 processor written in SpinalHDL

Yet Another Tetris on FPGA Implementation

Must-have verilog systemverilog modules