512 Open source projects that are alternatives of or similar to simple-riscv

List of ideas for getting started with TimVideos projects

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

SPI master and slave for FPGA written in VHDL

LicheeTang 蜂鸟E203 Core

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Compact FPGA game console

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

👇 Add capacitive touch buttons to any FPGA!

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Scala based HDL

Image Processing Toolbox in Verilog using Basys3 FPGA

AES-128 hardware implementation

FPGA-based RISC-V CPU+SoC.

SweRV EL2 Core

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A Forth CPU and System on a Chip, based on the J1, written in VHDL

Tools for running FPGA vendor toolchains with Docker

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

Docker Development Environment for SpinalHDL

HDMI Out VHDL code for 7-series Xilinx FPGAs

SpinalHDL - Cryptography libraries

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

RISC-V Cores, SoC platforms and SoCs

VUnit is a unit testing framework for VHDL/SystemVerilog

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

Haskell to VHDL/Verilog/SystemVerilog compiler

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

A FPGA friendly 32 bit RISC-V CPU implementation

SweRV EH1 core

Implementations of the Simon and Speck Block Ciphers

A reimplementation of a tiny stack CPU

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Caffe to VHDL

An open-source VHDL library for FPGA design.

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Space Invaders game implemented with VHDL

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

This repository contains synthesizable examples which use the PoC-Library.

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Homebrew game for homebrew FPGA game console

32-bit Superscalar RISC-V CPU

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Cross EDA Abstraction and Automation

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Yet Another RISC-V Implementation

RISC-V Cores, SoC platforms and SoCs

RISC-V CPU Core (RV32IM)

HAL – The Hardware Analyzer

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

No-MMU Linux capable RISC-V SoC designed to be useful.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

A JSON library implemented in VHDL.