KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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Mutual labels: cpu, fpga, riscv, verilog

Cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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Mutual labels: fpga, cpu, riscv

Fpga101 Workshop

FPGA 101 - Workshop materials

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Mutual labels: verilog, fpga, riscv

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

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Mutual labels: fpga, rtl, verilog

getting-started

List of ideas for getting started with TimVideos projects

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Mutual labels: fpga, verilog, risc-v

Riscv Fs

F# RISC-V Instruction Set formal specification

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Mutual labels: cpu, risc-v, riscv

Riscboy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

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Mutual labels: fpga, cpu, risc-v

Verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

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Mutual labels: verilog, fpga, rtl

J1sc

A reimplementation of a tiny stack CPU

Stars: ✭ 64 (-16.88%)

Mutual labels: verilog, fpga, cpu

Icestation 32

Compact FPGA game console

Stars: ✭ 93 (+20.78%)

Mutual labels: verilog, fpga, risc-v

E200 opensource

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

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Mutual labels: verilog, cpu, risc-v

drec-fpga-intro

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

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Mutual labels: fpga, verilog, risc-v

Logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

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Mutual labels: verilog, fpga, rtl

Fpga readings

Recipe for FPGA cooking

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Mutual labels: verilog, fpga, rtl

SpinalDev

Docker Development Environment for SpinalHDL

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Mutual labels: fpga, rtl, verilog

spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

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Mutual labels: fpga, verilog, risc-v

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

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Mutual labels: fpga, rtl, verilog

Platformio Core

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

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Mutual labels: verilog, fpga, risc-v

tree-core-cpu

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Stars: ✭ 22 (-71.43%)

Mutual labels: cpu, riscv, rtl

Zipcpu

A small, light weight, RISC CPU soft core

Stars: ✭ 640 (+731.17%)

Mutual labels: verilog, fpga, cpu

Rggen

Code generation tool for configuration and status registers

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Mutual labels: verilog, fpga, rtl

Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

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Mutual labels: cpu, fpga, riscv

blarney

Haskell library for hardware description

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Mutual labels: fpga, rtl, verilog

yatcpu

Yet another toy CPU.

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Mutual labels: cpu, riscv, risc-v

Spinalhdl

Scala based HDL

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Mutual labels: verilog, fpga, rtl

Tang e203 mini

LicheeTang 蜂鸟E203 Core

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Mutual labels: verilog, fpga, risc-v

Hard-JPEG-LS

FPGA-based JPEG-LS image compressor.

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Mutual labels: fpga, rtl, verilog

Chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

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Mutual labels: risc-v, riscv, rtl

Hrm Cpu

Human Resource Machine - CPU Design #HRM

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Mutual labels: verilog, fpga, cpu

FPGA-USB-Device

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

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Mutual labels: fpga, rtl, verilog

super-miyamoto-sprint

Homebrew game for homebrew FPGA game console

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Mutual labels: fpga, verilog, risc-v

Fake-SDcard

Imitate SDcard using FPGAs.

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Mutual labels: fpga, rtl, verilog

Cores

Various HDL (Verilog) IP Cores

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Mutual labels: verilog, fpga, rtl

virtio

Virtio implementation in SystemVerilog

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Mutual labels: fpga, rtl, verilog

cnn open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

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Mutual labels: fpga, rtl, verilog

SpinalCrypto

SpinalHDL - Cryptography libraries

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Mutual labels: fpga, rtl, verilog

vga-clock

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

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Mutual labels: fpga, rtl, verilog

KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

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Mutual labels: fpga, riscv, risc-v

Riscv Rust

RISC-V processor emulator written in Rust+WASM

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Mutual labels: cpu, risc-v, riscv

Mips Cpu

A MIPS CPU implemented in Verilog

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Mutual labels: verilog, fpga, cpu

Shecc

A self-hosting and educational C compiler

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Mutual labels: risc-v, riscv

Lbforth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

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Mutual labels: risc-v, riscv

Openpiton

The OpenPiton Platform

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Mutual labels: verilog, fpga

Openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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Mutual labels: verilog, rtl

Reduceron

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

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Mutual labels: verilog, fpga

Beagle sdr gps

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

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Mutual labels: verilog, fpga

Jt gng

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

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Mutual labels: verilog, fpga

Icezum

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

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Mutual labels: verilog, fpga

Jupiter

RISC-V Assembler and Runtime Simulator

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Mutual labels: risc-v, riscv

Fpga Imaging Library

An open source library for image processing on FPGA.