468 Open source projects that are alternatives of or similar to vboard

FPGA-based HDMI ambient lighting

Human Resource Machine - CPU Design #HRM

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

FuseSoC standard core library

Interface for MSX to Connect and use Raspberry Pi resources

My solutions to Alteras example labs

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

GBA on FPGA

Featherweight RISC-V implementation

冯爱民老师《计算机组成原理A》课程设计

Generator of verilog description for FPGA MobileNet implementation

Realtime VGA to ASCII Art converter

VCD file (Value Change Dump) command line viewer

Various projects for the Nexys4DDR board from Digilent

NES in Verilog

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

A list of VHDL codes implementing cryptographic algorithms

VHDL-Mips-Pipeline-Microprocessor

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

SystemVerilog language server

FPGA/AES/LeNet/VGG16

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

This repository contains synthesizable examples which use the PoC-Library.

A simple RISC-V processor for use in FPGA designs.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

CNN accelerator

VHDL-2008 Support Library

Connectal is a framework for software-driven hardware development.

Contains examples to start with Kactus2.

Experimental compiler for a subset of Haskell to VHDL

Verilog version of Z-scale (deprecated)

collaboration on work in progress

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

Verilog implementation of the SHA-512 hash function.

SDRAM controller with multiple wishbone slave ports

A VHDL frontend for Yosys

High Speed Analog Front End FPGA Firmware for Novena PVT1

An open-source VHDL library for FPGA design.

A programming language for FPGAs.

i8080 precise replica in Verilog, based on reverse engineering of real die

Simple custom computer on a FPGA

Core description files for FuseSoC

A demonstration showing how several components can be compsed to build a simulated spectrogram

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

OpenN@S: Open-source software to NAS automatic VHDL code generation

mystorm sram test

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

AXI PSRAM Controller IP for use with Digilent Nexys 4

Test suite designed to check compliance with the SystemVerilog standard.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

AES-128 hardware implementation

A utility for Composing FPGA designs from Peripherals

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.