468 Open source projects that are alternatives of or similar to vboard

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Virtio implementation in SystemVerilog

Facilitates building open source tools for working with hardware description languages (HDLs)

Scripts to build and use docker images including GHDL

Trying to verify Verilog/VHDL designs with formal methods and tools

HDL symbol generator

Cross EDA Abstraction and Automation

A FPGA friendly 32 bit RISC-V CPU implementation

Revengineered ancient PDP-11 CPUs, originals and clones

PCIe (1.0a to 2.0) Virtual host model for verilog

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Test suite designed to check compliance with the SystemVerilog standard.

SpinalHDL - Cryptography libraries

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Image Processing Toolbox in Verilog using Basys3 FPGA

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Video Game custom chips reverse-engineered from silicon

Yet Another VHDL tool

A configurable C++ generator of pipelined Verilog FFT cores

Tools for running FPGA vendor toolchains with Docker

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A collection of debugging busses developed and presented at zipcpu.com

Hardware Description Languages

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Scala based HDL

Sphinx Extension which generates various types of diagrams from Verilog code.

An abstraction library for interfacing EDA tools

A tiny Open POWER ISA softcore written in VHDL 2008

A List of Free and Open Source Hardware Verification Tools and Frameworks

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Bazel build rules for Verilator

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

A collection of phase locked loop (PLL) related projects

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Wishbone controlled I2C controllers

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

A reimplementation of a tiny stack CPU

Repurposing existing HDL tools to help writing better code

List of ideas for getting started with TimVideos projects

Docker Development Environment for SpinalHDL

A JSON library implemented in VHDL.

Haskell to VHDL/Verilog/SystemVerilog compiler

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Open source software for chip reverse engineering.

👇 Add capacitive touch buttons to any FPGA!

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Yet Another Tetris on FPGA Implementation

MOS6581 SID chip emulator in SystemVerilog

VHDL formatter web online written in typescript

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

@elahe-dastan / @1995parham training and testing repository 📚 🤓

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

Interface for MSX to Connect and use Raspberry Pi resources

Generator of verilog description for FPGA MobileNet implementation

AXI support for Migen/MiSoC

A Hardware Construct Language

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.