345 Open source projects that are alternatives of or similar to vcdvcd

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Must-have verilog systemverilog modules

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Virtio implementation in SystemVerilog

Docker Development Environment for SpinalHDL

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

An open source SPI flash emulator and monitor

A High-performance Timing Analysis Tool for VLSI Systems

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

ggplot everything

SpinalHDL - Cryptography libraries

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

A Hardware Construct Language

A collection of debugging busses developed and presented at zipcpu.com

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

A litecoin scrypt miner implemented with FPGA on-chip memory.

Lattice iCE40: development platform for PlatformIO

synthesiseable ieee 754 floating point library in verilog

Simple 3-stage pipeline RISC-V processor

32-bit Superscalar RISC-V CPU

A programming language for FPGAs.

A Verilog HDL model of the MOS 6502 CPU

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Sphinx Extension which generates various types of diagrams from Verilog code.

Virtual development board for HDL design

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Facilitates building open source tools for working with hardware description languages (HDLs)

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

Generator of verilog description for FPGA MobileNet implementation

Tools for running FPGA vendor toolchains with Docker

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

NN on FPGA

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Open source implementation of a x86 processor

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

PDP-6 Emulator

FPGA-based Nintendo Entertainment System Emulator

Small footprint and configurable PCIe core

Programmable multichannel ADPCM decoder for FPGA

Notes on the Red Pitaya Open Source Instrument

MOS6581 SID chip emulator in SystemVerilog

Cross EDA Abstraction and Automation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

A formally verified high-level synthesis tool based on CompCert and written in Coq.

FPGA-based JPEG-LS image compressor.

FAST-9 Accelerator for Corner Detection

Yet Another Tetris on FPGA Implementation