143 Open source projects that are alternatives of or similar to Yodl

VHDL Package for Sublime Text

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

VHDL-Mips-Pipeline-Microprocessor

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

Xilinx Deep Learning IP

Scripts to build and use docker images including GHDL

Experimental compiler for a subset of Haskell to VHDL

VCD file (Value Change Dump) command line viewer

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

A list of VHDL codes implementing cryptographic algorithms

AXI PSRAM Controller IP for use with Digilent Nexys 4

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

A pipelined RISCV implementation in VHDL

This repository contains synthesizable examples which use the PoC-Library.

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

VHDL-2008 Support Library

A FPGA friendly 32 bit RISC-V CPU implementation

A JSON library implemented in VHDL.

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

HDL symbol generator

Implementations of the Simon and Speck Block Ciphers

An open-source VHDL library for FPGA design.

A Audio Interface for the Zedboard

Yet Another VHDL tool

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

OpenN@S: Open-source software to NAS automatic VHDL code generation

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

Virtual development board for HDL design

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

SpinalHDL - Cryptography libraries

An implementation of original SHA-256 hash function in (RTL) VHDL

HDMI Out VHDL code for 7-series Xilinx FPGAs

VHDL Samples

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A work-in-progress for what is to be a software-free web server for static content.

👇 Add capacitive touch buttons to any FPGA!

Yet Another Forth Core...

@elahe-dastan / @1995parham training and testing repository 📚 🤓

Scala based HDL

Interface for MSX to Connect and use Raspberry Pi resources

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

Docker Development Environment for SpinalHDL

VUnit is a unit testing framework for VHDL/SystemVerilog

RISC-V by VectorBlox

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

GameCube Digital AV converter

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

An implementation of DisplayPort protocol for FPGAs

Community created parallella projects

A simple RISC-V processor for use in FPGA designs.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

This repository is the backup of XJTU-Tripler project, participating dac19 system design contest

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.

27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting

Haskell to VHDL/Verilog/SystemVerilog compiler

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz