574 Open source projects that are alternatives of or similar to Cores Swerv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SweRV EL2 Core

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

FPGA-based RISC-V CPU+SoC.

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Quasar 2.0: Chisel equivalent of SweRV-EL2

ARV: Asynchronous RISC-V Go High-level Functional Model

RISC-V processor emulator written in Rust+WASM

Yet Another RISC-V Implementation

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

RISC-V Instruction Set Metadata

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Various HDL (Verilog) IP Cores

Small Processing Unit 32: A compact RV32I CPU written in Verilog

SoC based on VexRiscv and ICE40 UP5K

SystemOT, yet another home brew cpu.

Nuclei RISC-V Software Development Kit

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

SpinalHDL - Cryptography libraries

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

Imitate SDcard using FPGAs.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

The OpenPiton Platform

Shakti: development platform for PlatformIO

RISC-V CPU Core (RV32IM)

Maxine VM: A meta-circular research VM

Docker Development Environment for SpinalHDL

Virtio implementation in SystemVerilog

RISC-V Cores, SoC platforms and SoCs

Sphinx Extension which generates various types of diagrams from Verilog code.

No-MMU Linux capable RISC-V SoC designed to be useful.

FPGA-based JPEG-LS image compressor.

RISC-V RV32I[MAC] emulator with ELF support

A Forth CPU and System on a Chip, based on the J1, written in VHDL

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Haskell library for hardware description

Simple risc-v emulator, able to run linux, written in C.

Nuclei Microcontroller Software Interface Standard Development Repo

Sedna - a pure Java RISC-V emulator.

EVEREST: e-Versatile Research Stick for peoples

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A RISC-V simulator

List of ideas for getting started with TimVideos projects

MDEPX — A BSD-style RTOS

RISCV SoftCPU Contest 2018

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

RISC-V Assembler and Runtime Simulator

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Homebrew game for homebrew FPGA game console

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication