437 Open source projects that are alternatives of or similar to DFiant

Video Game custom chips reverse-engineered from silicon

ACT hardware description language and core tools.

HW Design: A Functional Approach

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Code generation tool for configuration and status registers

Haskell to VHDL/Verilog/SystemVerilog compiler

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

A visual systems language for beginners compiled using LLVM

RISC-V CPU Core (RV32IM)

RISC-V Cores, SoC platforms and SoCs

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Sphinx Extension which generates various types of diagrams from Verilog code.

SystemRDL 2.0 language compiler front-end

A curated list of awesome open source hardware design tools

Web-based HDL diagramming tool

Workflows and interfaces for neuroimaging packages

The RaftLib C++ library, streaming/dataflow concurrency via C++ iostream-like operators

Various HDL (Verilog) IP Cores

Simple flow library 🖥️🖱️

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

The Refreshingly Simple Cross-Platform C++ Dataflow / Pipelining / Stream Processing / Reactive Programming Framework

Dnai Editor - Visual Scripting (Node Editor)

FPGA CryptoNight V7 Minner

RISC-V Cores, SoC platforms and SoCs

VUnit is a unit testing framework for VHDL/SystemVerilog

Dataflow compiler for QNN inference on FPGAs

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Virtio implementation in SystemVerilog

This repository contains iCEBreaker examples for Amaranth HDL.

32-bit Superscalar RISC-V CPU

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

shdl6800: A 6800 processor written in SpinalHDL

Import and export IP-XACT XML register models

An inter-language runtime for flow-based programming (FBP)

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

Cross EDA Abstraction and Automation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Generate UVM register model from compiled SystemRDL input

A configurable C++ generator of pipelined Verilog FFT cores

RISCV SoftCPU Contest 2018

Build a real-time website analytics dashboard on GCP using Dataflow, Cloud Memorystore (Redis) and Spring Boot

Pothos demonstration applications

Repository gathering basic modules for CDC purpose

Functional dataflow through composable computations

A general framework for optimizing DNN dataflow on systolic array

Antmicro's fast, vendor-neutral DMA IP in Chisel

Project X-Ray Database: XC7 Series

Cluster computing using Stateful Dataflow Graphs

🌟 Alhambra II FPGA board

Cocoon – a flow-based workflow automation, data mining and visual analytics tool.

A scalable High-Level Synthesis framework on MLIR

DDC/DUC SDR Tranceiver project

A low cost FPGA development board for absolute newbies

zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Project F brings FPGAs to life with exciting open-source designs you can build on.

FPGA core for SHA256d mining targeting Lattice iCE40 devices.