479 Open source projects that are alternatives of or similar to formal_hw_verification

Scripts to build and use docker images including GHDL

Virtual development board for HDL design

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

SpinalHDL - Cryptography libraries

HDL symbol generator

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Scala based HDL

Haskell to VHDL/Verilog/SystemVerilog compiler

Sphinx Extension which generates various types of diagrams from Verilog code.

A JSON library implemented in VHDL.

Reads a state transition system and performs property checking

A reimplementation of a tiny stack CPU

Hardware Description Languages

A tiny Open POWER ISA softcore written in VHDL 2008

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

A FPGA friendly 32 bit RISC-V CPU implementation

List of ideas for getting started with TimVideos projects

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Cross EDA Abstraction and Automation

An abstraction library for interfacing EDA tools

A List of Free and Open Source Hardware Verification Tools and Frameworks

Repurposing existing HDL tools to help writing better code

Open source software for chip reverse engineering.

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Docker Development Environment for SpinalHDL

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Image Processing Toolbox in Verilog using Basys3 FPGA

Tools for running FPGA vendor toolchains with Docker

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A simple I2C minion in VHDL

FAST-9 Accelerator for Corner Detection

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

PDP-6 Emulator

An exhaustive list of all Rust resources regarding automated or semi-automated formalization efforts in any area, constructive mathematics, formal algorithms, and program verification.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

FPGA-based JPEG-LS image compressor.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

NN on FPGA

Virtio implementation in SystemVerilog

Facilitates building open source tools for working with hardware description languages (HDLs)

A Hardware Construct Language

Simple implementation of cache using VHDL

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Lattice iCE40: development platform for PlatformIO

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Yet Another RISC-V Implementation

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Generator of verilog description for FPGA MobileNet implementation

Fully proved small C functions (examples for verification course).

Formalization of Tendermint proposer election properties