ReduceronFPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
Stars: ✭ 308 (-5.23%)
dpllA collection of phase locked loop (PLL) related projects
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SpinalCryptoSpinalHDL - Cryptography libraries
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Icezum🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
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LVDS-7-to-1-SerializerAn Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
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ZYNQ-NVDLANVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
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FpOCFPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
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xedaCross EDA Abstraction and Automation
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blarneyHaskell library for hardware description
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yahdlA programming language for FPGAs.
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RiscvRISC-V CPU Core (RV32IM)
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ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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CoresVarious HDL (Verilog) IP Cores
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EdalizeAn abstraction library for interfacing EDA tools
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virtioVirtio implementation in SystemVerilog
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rapcoresRobotic Application Processor
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Deep-DarkFantasyGlobal Dark Mode for ALL apps on ANY platforms.
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karutaKaruta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
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wbi2cWishbone controlled I2C controllers
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mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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yafpgatetrisYet Another Tetris on FPGA Implementation
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Beagle sdr gpsKiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
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FPGA ThreeLevelStorage【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Stars: ✭ 86 (-73.54%)
VerilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
Stars: ✭ 296 (-8.92%)
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
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gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
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vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
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Speech256An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
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spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
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MobileNet-in-FPGAGenerator of verilog description for FPGA MobileNet implementation
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async fifoA dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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VGChipsVideo Game custom chips reverse-engineered from silicon
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kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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yarviYet Another RISC-V Implementation
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veriflaFork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
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EDSACFPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
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fpga-nnNN on FPGA
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FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
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Fake-SDcardImitate SDcard using FPGAs.
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1bitSDRMinimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
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pdp6PDP-6 Emulator
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dblclockfftA configurable C++ generator of pipelined Verilog FFT cores
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usbcorevA full-speed device-side USB peripheral core written in Verilog.
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shapool-coreFPGA core for SHA256d mining targeting Lattice iCE40 devices.
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FPGA NTP SERVERA FPGA implementation of the NTP and NTS protocols
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fpga-dockerTools for running FPGA vendor toolchains with Docker
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SpinalDevDocker Development Environment for SpinalHDL
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Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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eddr3mirror of https://git.elphel.com/Elphel/eddr3
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getting-startedList of ideas for getting started with TimVideos projects
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OpenpitonThe OpenPiton Platform
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