A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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Mutual labels: rtl, verilator

Cores

Various HDL (Verilog) IP Cores

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cnn open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

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dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

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wbi2c

Wishbone controlled I2C controllers

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docker

Scripts to build and use docker images including GHDL

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OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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Ustc Rvsoc

FPGA-based RISC-V CPU+SoC.

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SpinalCrypto

SpinalHDL - Cryptography libraries

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Fpga readings

Recipe for FPGA cooking

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Rggen

Code generation tool for configuration and status registers

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vga-clock

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

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cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

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Mutual labels: verilog, hdl

Chisel3

Chisel 3: A Modern Hardware Design Language

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Mutual labels: rtl, verilog

Speech256

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

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Mutual labels: verilog, hdl

Sv Tests

Test suite designed to check compliance with the SystemVerilog standard.

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hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

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Mutual labels: rtl, verilog

SpinalDev

Docker Development Environment for SpinalHDL

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blarney

Haskell library for hardware description

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ofdm

Chisel Things for OFDM

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Mutual labels: rtl, verilog

xeda

Cross EDA Abstraction and Automation

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Mutual labels: verilog, hdl

dbgbus

A collection of debugging busses developed and presented at zipcpu.com

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Mutual labels: verilog, verilator

Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

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Darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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Openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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Mutual labels: rtl, verilog

Scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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Mutual labels: rtl, verilog

Verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

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Openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

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async fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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FPGA-USB-Device

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

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symbolator

HDL symbol generator

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rules verilator

Bazel build rules for Verilator

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Logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

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Mutual labels: rtl, verilog

cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

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VGChips

Video Game custom chips reverse-engineered from silicon

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dpll

A collection of phase locked loop (PLL) related projects

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Hard-JPEG-LS

FPGA-based JPEG-LS image compressor.

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OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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PyChip-py-hcl

A Hardware Construct Language

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Fake-SDcard

Imitate SDcard using FPGAs.

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Spinalhdl

Scala based HDL