545 Open source projects that are alternatives of or similar to Hdl_checker

A List of Free and Open Source Hardware Verification Tools and Frameworks

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Virtual development board for HDL design

Scripts to build and use docker images including GHDL

SystemVerilog language server

Tools for running FPGA vendor toolchains with Docker

Hardware Description Languages

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

List of ideas for getting started with TimVideos projects

Cross EDA Abstraction and Automation

A reimplementation of a tiny stack CPU

Docker Development Environment for SpinalHDL

A tiny Open POWER ISA softcore written in VHDL 2008

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

HDL symbol generator

An abstraction library for interfacing EDA tools

Haskell to VHDL/Verilog/SystemVerilog compiler

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

SpinalHDL - Cryptography libraries

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Trying to verify Verilog/VHDL designs with formal methods and tools

Scala based HDL

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Open source software for chip reverse engineering.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Image Processing Toolbox in Verilog using Basys3 FPGA

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL 2008/93/87 simulator

Light-weight RISC-V RV32IMC microcontroller core.

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.

Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project

A Video display simulator

Xilinx Deep Learning IP

IC design and development should be faster，simpler and more reliable

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Bitcoin miner for Xilinx FPGAs

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

PromQL language server

A Ruby language server.

A single-wire bi-directional chip-to-chip interface for FPGAs

ENSIME JVM Process

A very primitive but hopefully self-educational CPU in Verilog

Homotopy theory in Coq.

Pano Logic G2 Reverse Engineering Project

Ham Radio hat for Raspberry PI

FPGA-based C64 Accelerator / C65 like computer

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Compact FPGA game console

Language server for PHP, with powerful static analysis and type inference.

FPGA-based RISC-V CPU+SoC.

Verilog module for calculation of FFT.

SystemVerilog linter

GPGPU microprocessor architecture

FuseSoC-based SoC for SweRV EH1