ElectronA mixed signal netlist language (pre-alpha)
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dpllA collection of phase locked loop (PLL) related projects
Stars: ✭ 55 (-80.36%)
Fake-SDcardImitate SDcard using FPGAs.
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kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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CoresVarious HDL (Verilog) IP Cores
Stars: ✭ 271 (-3.21%)
gateware-tsHardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
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virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (-86.43%)
ZYNQ-NVDLANVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
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fpga-nnNN on FPGA
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EdalizeAn abstraction library for interfacing EDA tools
Stars: ✭ 270 (-3.57%)
Speech256An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
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SpinalDevDocker Development Environment for SpinalHDL
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yafpgatetrisYet Another Tetris on FPGA Implementation
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vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (-82.86%)
rapcoresRobotic Application Processor
Stars: ✭ 14 (-95%)
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
Stars: ✭ 29 (-89.64%)
xedaCross EDA Abstraction and Automation
Stars: ✭ 25 (-91.07%)
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (-48.21%)
Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
Stars: ✭ 52 (-81.43%)
EDSACFPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
Stars: ✭ 28 (-90%)
veriflaFork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
Stars: ✭ 21 (-92.5%)
wbi2cWishbone controlled I2C controllers
Stars: ✭ 25 (-91.07%)
dblclockfftA configurable C++ generator of pipelined Verilog FFT cores
Stars: ✭ 147 (-47.5%)
shapool-coreFPGA core for SHA256d mining targeting Lattice iCE40 devices.
Stars: ✭ 19 (-93.21%)
intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Stars: ✭ 43 (-84.64%)
fpga-dockerTools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (-80.71%)
Raemixx500Open Hardware Remake of the Commodore Amiga 500+ Mainboard
Stars: ✭ 161 (-42.5%)
FPGA ThreeLevelStorage【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Stars: ✭ 86 (-69.29%)
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (+16.07%)
VGChipsVideo Game custom chips reverse-engineered from silicon
Stars: ✭ 86 (-69.29%)
Basic verilogMust-have verilog systemverilog modules
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drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
Stars: ✭ 66 (-76.43%)
ics-adpcmProgrammable multichannel ADPCM decoder for FPGA
Stars: ✭ 18 (-93.57%)
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (-43.93%)
yahdlA programming language for FPGAs.
Stars: ✭ 20 (-92.86%)
spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
Stars: ✭ 51 (-81.79%)
Deep-DarkFantasyGlobal Dark Mode for ALL apps on ANY platforms.
Stars: ✭ 16 (-94.29%)
1bitSDRMinimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
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SpinalCryptoSpinalHDL - Cryptography libraries
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pdp6PDP-6 Emulator
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MobileNet-in-FPGAGenerator of verilog description for FPGA MobileNet implementation
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yarviYet Another RISC-V Implementation
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karutaKaruta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Stars: ✭ 89 (-68.21%)
async fifoA dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Stars: ✭ 117 (-58.21%)
usbcorevA full-speed device-side USB peripheral core written in Verilog.
Stars: ✭ 135 (-51.79%)
FPGA NTP SERVERA FPGA implementation of the NTP and NTS protocols
Stars: ✭ 27 (-90.36%)
mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
Stars: ✭ 15 (-94.64%)
eddr3mirror of https://git.elphel.com/Elphel/eddr3
Stars: ✭ 33 (-88.21%)
RiscvRISC-V CPU Core (RV32IM)
Stars: ✭ 272 (-2.86%)
Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
Stars: ✭ 205 (-26.79%)
Biriscv32-bit Superscalar RISC-V CPU
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LVDS-7-to-1-SerializerAn Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
Stars: ✭ 33 (-88.21%)
FpOCFPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
Stars: ✭ 138 (-50.71%)
getting-startedList of ideas for getting started with TimVideos projects
Stars: ✭ 50 (-82.14%)