The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Stars: ✭ 79 (-79.37%)

Mutual labels: processor, verilog

Clash Compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Stars: ✭ 958 (+150.13%)

Mutual labels: verilog, vhdl

Edalize

An abstraction library for interfacing EDA tools

Stars: ✭ 270 (-29.5%)

Mutual labels: verilog, vhdl

Openpiton

The OpenPiton Platform

Stars: ✭ 282 (-26.37%)

Mutual labels: verilog, processor

Awesome Open Hardware Verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

Stars: ✭ 103 (-73.11%)

Mutual labels: verilog, vhdl

fpga-docker

Tools for running FPGA vendor toolchains with Docker

Stars: ✭ 54 (-85.9%)

Mutual labels: vhdl, verilog

getting-started

List of ideas for getting started with TimVideos projects

Stars: ✭ 50 (-86.95%)

Mutual labels: vhdl, verilog

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Stars: ✭ 46 (-87.99%)

Mutual labels: vhdl, verilog

docker

Scripts to build and use docker images including GHDL

Stars: ✭ 27 (-92.95%)

Mutual labels: vhdl, verilog

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Stars: ✭ 325 (-15.14%)

Mutual labels: vhdl, verilog

Darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Stars: ✭ 1,062 (+177.28%)

Mutual labels: verilog, processor

J1sc

A reimplementation of a tiny stack CPU

Stars: ✭ 64 (-83.29%)

Mutual labels: verilog, vhdl

SpinalDev

Docker Development Environment for SpinalHDL

Stars: ✭ 17 (-95.56%)

Mutual labels: vhdl, verilog

Tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Stars: ✭ 153 (-60.05%)

Mutual labels: verilog, vhdl

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Stars: ✭ 59 (-84.6%)

Mutual labels: vhdl, verilog

formal hw verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Stars: ✭ 32 (-91.64%)

Mutual labels: vhdl, verilog

intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Stars: ✭ 43 (-88.77%)

Mutual labels: vhdl, verilog

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Stars: ✭ 20 (-94.78%)

Mutual labels: vhdl, verilog

vboard

Virtual development board for HDL design

Stars: ✭ 32 (-91.64%)

Mutual labels: vhdl, verilog

Potato

A simple RISC-V processor for use in FPGA designs.

Stars: ✭ 181 (-52.74%)

Mutual labels: vhdl, processor

SpinalCrypto

SpinalHDL - Cryptography libraries

Stars: ✭ 36 (-90.6%)

Mutual labels: vhdl, verilog

Ophidian

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Stars: ✭ 32 (-91.64%)

Mutual labels: verilog, vhdl

Vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

Stars: ✭ 1,041 (+171.8%)

Mutual labels: verilog, vhdl

Cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Stars: ✭ 740 (+93.21%)

Mutual labels: verilog, vhdl

xeda

Cross EDA Abstraction and Automation

Stars: ✭ 25 (-93.47%)

Mutual labels: vhdl, verilog

symbolator

HDL symbol generator

Stars: ✭ 123 (-67.89%)

Mutual labels: vhdl, verilog

math

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Stars: ✭ 15 (-96.08%)

Mutual labels: vhdl, verilog

Opl3 fpga

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

Stars: ✭ 255 (-33.42%)

Mutual labels: vhdl

Beagle sdr gps

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Stars: ✭ 300 (-21.67%)

Mutual labels: verilog

Riscv Rust

RISC-V processor emulator written in Rust+WASM

Stars: ✭ 253 (-33.94%)

Mutual labels: processor

Fake-SDcard

Imitate SDcard using FPGAs.

Stars: ✭ 26 (-93.21%)

Mutual labels: verilog

F32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Stars: ✭ 338 (-11.75%)

Mutual labels: vhdl

Verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Stars: ✭ 296 (-22.72%)

Mutual labels: verilog

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Stars: ✭ 148 (-61.36%)

Mutual labels: verilog

blarney

Haskell library for hardware description

Stars: ✭ 81 (-78.85%)

Mutual labels: verilog

Hal

HAL – The Hardware Analyzer

Stars: ✭ 298 (-22.19%)

Mutual labels: vhdl

Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

Stars: ✭ 19 (-95.04%)

Mutual labels: processor

simple-riscv

A simple three-stage RISC-V CPU

Stars: ✭ 14 (-96.34%)

Mutual labels: vhdl

Riscv vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Stars: ✭ 356 (-7.05%)

Mutual labels: vhdl

Dsi Shield

Arduino MIPI DSI Shield

Stars: ✭ 330 (-13.84%)

Mutual labels: vhdl

Openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Stars: ✭ 293 (-23.5%)

Mutual labels: verilog

32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

Stars: ✭ 66 (-82.77%)

Mutual labels: verilog

ofdm

Chisel Things for OFDM

Stars: ✭ 23 (-93.99%)

Mutual labels: verilog

Verilogboy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Stars: ✭ 287 (-25.07%)

Mutual labels: verilog

SmartVHDL

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)