1021 Open source projects that are alternatives of or similar to Reduceron

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

An abstraction library for interfacing EDA tools

Haskell library for hardware description

Lattice iCE40: development platform for PlatformIO

Repository for basic (and not so basic) Verilog blocks with high re-use potential

SpinalHDL - Cryptography libraries

A configurable C++ generator of pipelined Verilog FFT cores

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Cross EDA Abstraction and Automation

Video Game custom chips reverse-engineered from silicon

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Dataflow compiler for QNN inference on FPGAs

A programming language for FPGAs.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

NN on FPGA

Virtio implementation in SystemVerilog

The OpenPiton Platform

A FPGA implementation of the NTP and NTS protocols

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Wishbone controlled I2C controllers

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Robotic Application Processor

Yet Another Tetris on FPGA Implementation

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Various HDL (Verilog) IP Cores

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Programmable multichannel ADPCM decoder for FPGA

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

MOS6581 SID chip emulator in SystemVerilog

Sphinx Extension which generates various types of diagrams from Verilog code.

Generator of verilog description for FPGA MobileNet implementation

Small Processing Unit 32: A compact RV32I CPU written in Verilog

PDP-6 Emulator

FPGA-based JPEG-LS image compressor.

Yet Another RISC-V Implementation

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

mirror of https://git.elphel.com/Elphel/eddr3

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A full-speed device-side USB peripheral core written in Verilog.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Imitate SDcard using FPGAs.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

RISC-V CPU Core (RV32IM)

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

A collection of phase locked loop (PLL) related projects

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Tools for running FPGA vendor toolchains with Docker

Docker Development Environment for SpinalHDL

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

List of ideas for getting started with TimVideos projects

Homebrew game for homebrew FPGA game console

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.