426 Open source projects that are alternatives of or similar to vhdl-hdmi-out

List of ideas for getting started with TimVideos projects

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

HAL – The Hardware Analyzer

Space Invaders game implemented with VHDL

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

SPI master and slave for FPGA written in VHDL

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

A reimplementation of a tiny stack CPU

VUnit is a unit testing framework for VHDL/SystemVerilog

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

An abstraction library for interfacing EDA tools

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

An open-source VHDL library for FPGA design.

A JSON library implemented in VHDL.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Scala based HDL

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

A FPGA friendly 32 bit RISC-V CPU implementation

Haskell to VHDL/Verilog/SystemVerilog compiler

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

Docker Development Environment for SpinalHDL

Cross EDA Abstraction and Automation

Tools for running FPGA vendor toolchains with Docker

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

AES-128 hardware implementation

A Forth CPU and System on a Chip, based on the J1, written in VHDL

Caffe to VHDL

Image Processing Toolbox in Verilog using Basys3 FPGA

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

SpinalHDL - Cryptography libraries

This repository contains synthesizable examples which use the PoC-Library.

A simple three-stage RISC-V CPU

Implementations of the Simon and Speck Block Ciphers

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

👇 Add capacitive touch buttons to any FPGA!

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Universal HDMI/DVI Displays with Touch Panel for Raspberry Pi, BeagleBone, ODROID, UDOO...

Kansas Lava implementation of MOS 6502 microprocessor

Yet Another Tetris on FPGA Implementation

Virtio implementation in SystemVerilog

iCE40 floorplan viewer

VHDL formatter web online written in typescript

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

@elahe-dastan / @1995parham training and testing repository 📚 🤓

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

RISC-V Cores, SoC platforms and SoCs

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

SHA-256 IP core for ZedBoard (Zynq SoC)

This project demonstrates DSP capabilities of Terasic DE2-115

Interface for MSX to Connect and use Raspberry Pi resources

Polyphony is Python based High-Level Synthesis compiler.

No-MMU Linux capable RISC-V SoC designed to be useful.

The Task Parallel System Composer (TaPaSCo)