785 Open source projects that are alternatives of or similar to Zipcpu

A mixed signal netlist language (pre-alpha)

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

The Antikernel operating system project

GPGPU microprocessor architecture

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Connectal is a framework for software-driven hardware development.

i8080 precise replica in Verilog, based on reverse engineering of real die

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

LicheeTang 蜂鸟E203 Core

A simple, basic, formally verified UART controller

All open source file and project for OpenFPGAduino project

A wishbone controlled scope for FPGA's

CHIP-8 console on FPGA

Recipe for FPGA cooking

Verilog Generator of Neural Net Digit Detector for FPGA

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

The OpenPiton Platform

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Tools for running FPGA vendor toolchains with Docker

A collection of phase locked loop (PLL) related projects

Various HDL (Verilog) IP Cores

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Cross EDA Abstraction and Automation

Robotic Application Processor

Video Game custom chips reverse-engineered from silicon

Virtio implementation in SystemVerilog

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Sphinx Extension which generates various types of diagrams from Verilog code.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Generator of verilog description for FPGA MobileNet implementation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA-based JPEG-LS image compressor.

Lattice iCE40: development platform for PlatformIO

Haskell library for hardware description

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

PDP-6 Emulator

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A full-speed device-side USB peripheral core written in Verilog.

A FPGA implementation of the NTP and NTS protocols

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

mirror of https://git.elphel.com/Elphel/eddr3

List of ideas for getting started with TimVideos projects

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Global Dark Mode for ALL apps on ANY platforms.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Programmable multichannel ADPCM decoder for FPGA

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Homebrew game for homebrew FPGA game console